Hi,
I am using the open source IgH EtherCAT master v1.5.2 with some patches applied (see http sourceforge dot net /u/davepage/etherlabmaster/) and I have been experiencing a PRU hang and a DC problem. On my slave based on the ICE, the PRU hang causes the ARM to hang in bsp_send_command_to_firmware() waiting for the command response.
So, I returned to the ICE and trialed various versions of IDK code running under my master with DC configured. See below.
In summary. versions > 1.1.0.5 crash hard and > 1.1.0.4 the DC does not work.
And by not work I mean when it doesn't crash I can look a the time difference register and see small values (<200nsec), and the next SYNC0 registers are good, but the SYNC0 outputs do not occur when they are supposed to.
There is likely no fundamental problems with the master or application...
So, I am OK with the fact the the TI ESC is not completely complaint with the ET1100 implementation, so long as it is spec compliant. But the IgH master is also spec compliant -- there is not so much guidance in the spec as to how to initialize DC. Therefore, TI should either emulate the ET1x00 faithfully, or should document exactly what is acceptable in terms of a initialization procedure. Or, test the code with the masters in common use, and make it work. Or, provide the EtherCAT PRU code under NDA to entities requiring results.
For now, I revert my slave to 1.1.0.3, but if this doesn't get fixed in 1.1.0.7 I'm going to drop TI from my design and start over with one of your competitors. No reputable slave product vendor is going to ship an EtherCAT device that has master compatibility as poor as this.
Thanks - Dave
Revert to TI ICE dev board V1.0 with prebuilt firmware as a baseline case.
Pattern for old TI downloads:
Change version number, as needed. Works back to 01_00_00_09
Write SD/app file to SD card, insert and reboot.
Boot putty to USB serial 115200 for both cards and pushbutton reset
Verify intended version for trial from serial boot output
First slave
*** StarterWare Boot Loader. Build - ***
Copying application image from MMCSD to RAM
Copying to RAM completed successfully
Image Copy Successful, Executing Application..
TI Industrial SDK Version : IASDK 1.1.0.3
Device name : AM3359
Chip Revision : AM335x ES1.0 [PG1]
ARM Clock rate : 550
Device Type : EtherCAT Device
TI EtherCAT Demo Application Build - 3.4.0 - running on ICE
Copying application image from MMCSD to RAM
Copying to RAM completed successfully
Image Copy Successful, Executing Application..
TI Industrial SDK Version : IASDK 1.1.0.3
Device name : AM3359
Chip Revision : AM335x ES1.0 [PG1]
ARM Clock rate : 550
Device Type : EtherCAT Device
TI EtherCAT Demo Application Build - 3.4.0 - running on ICE
Second slave
*** StarterWare Boot Loader. Build -
Copying application image from MMCSD to RAM
Copying to RAM completed successfully
Image Copy Successful, Executing Application..
TI Industrial SDK Version : IASDK 1.1.0.3
Device name : AM3359
Chip Revision : AM335x ES1.0 [PG1]
ARM Clock rate : 600
Device Type : EtherCAT Device
TI EtherCAT Demo Application Build - 3.4.0 - running on ICE
Note: For some reason the first slave is running at 550MHz vs 600Mhz
First slave is an older board with 1.0A sticker
Second slave has a 1.0A silk screen
No idea whatsoever how they can both be exactly the same revision
Each trial consists of starting the master application (i.e. RUN mode) then stopping the application.
1.1.0.6 TI prebuilt SD/app
Pushbutton reset, wait for master to rescan complete
Trial 1 failed, both slaves show error flag
Trial 2 failed, both: Failed to set state INIT: No response.Performed a manual rescan. Both slaves show VID/PID 0:0 PREOP E (crashed)
Pushbutton reset, wait for master to rescan complete. Slaves show PREOP as expected
Trial 1 failed, both slaves show error flag
Performed a manual rescan. Both slaves show alias 65536 VID/PID 0:0 PREOP (crashed)
1.1.0.5 TI prebuilt SD/app
Pushbutton reset, wait for master to rescan complete
Trial 1 failed, both slaves show error flag
Performed a manual rescan. Both slaves show alias 65536 VID/PID 0:0 PREOP (crashed)
Trial discontinued1.1.0.4 TI prebuilt SD/app
Pushbutton reset, wait for master to rescan complete
Trial 1 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Trial 2 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Pushbutton reset, wait for master to rescan complete
Trial 3 Slaves boot OK, but SYNC0s drift in phase (not same frequency) Trial 4 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Trial 5 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Trial 6 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Trial 7 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Pushbutton reset, wait for master to rescan complete
Trial 8 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
Trial 9 Slaves boot OK, but SYNC0s drift in phase (not same frequency)
NOTE: slave-slave phase error appears bad (+/-2usec) after reset, and subsequent trials much worse (random)1.1.0.3 TI prebuilt SD/app
Pushbutton reset, wait for master to rescan complete
Trial 1 OK Quick lock; in phase 20nsec peak jitter slave to slaveTrial 2 OK
Trial 3 OK
Trial 4 OK
Trial 5 OK
Pushbutton reset, wait for master to rescan complete
Trial 6 OK
Trial 7 OK
Trial 8 OK
Trial 9 OK
Trial 10 OK
1.0.0.9 TI prebuilt SD/app
Pushbutton reset, wait for master to rescan complete
Trial 1 OK -- SYNC0 from each slaves appears in correct phase
Trial 2 OK
Trial 3 OK
Trial 4 OK
Trial 5 OK
Pushbutton reset, wait for master to rescan complete
Trial 6 OKTrial 7 OK
Trial 8 OK -- on exit saw 0x001A Synchronization Error
Trial 9 OK
Trial 10 OK
