Hi,
We are having a custom board of TCI6486 DSP. The EMAC1 interface is used for Ethernet with RGMII PHY. It is working at 1Gbps speed.
We have developed a code for supporting 1024 channel processing at a time. It include ethernet packet receive & some transmit in core0.
Major emac transmit and Tsip processing is divided among 4 other cores (1,2,3,4).
DDR2 memory in cacheable configuration is used for ethernet packet buffers. EMAC BD's are in L2.
L1P, L1D cache is enabled in all cores.
We are handling EMAC interrupts using csl library provided by TI.
EW_INTCTL register is cleared for the specific interrupt while inside the ISR.
SL2 and DDR memory cache coherence issue is taken care inside the code using cachewb and cacheinv wherever required.
The issue occurs on a very huge load on EMAC channel-0 i.e in core0, which is configured for Reception of packets.
When we pump a good load of rtp packets on to this RX channel, RX0HDP is getting zero as the packet reception rate is faster than the packet processing rate .
After this condition occurs EMAC will not be able to receive any packet and give trigger interrupt for processing the packets.
Now we need a solution to handle this event, even if it might result in dropping some packets so that EMAC Rx0HDP will not go to zero.
Or if we cannot restrict this from happening, can someone help us with Re-initializing HDP with the next free BD available as per Descriptor queue read_ptr value(According to TI library code) with out re-initializing EMAC with emac_open and emac_close calls.
