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C674x uPP DMA Window in DDR2

Hi.

The TRM describes "The window address can reside in any available memory space (including EMIF), but it must be aligned to a 64-bit boundary."

Does this mean the window can reside in DDR2 connected through EMIF as well?
And please tell me if you have any restrictions for the DDR2 case.

Best regards,
Tsutomu Furuse