GPMC Synchronous Access on AAD device, address stuck at 0

Hi,

Which processor is this? What is the software that you use?

Sorry, i totally forgot to mention that. It's an AM3359 and I'm using CCS 6.
I'm running the initialisation via GEL file and then access the "memory" (Cyclone V FPGA) via CCS 6 Memory Viewer.
I can monitor the actual access patterns via Signal Tap through the FPGA.

Do you enable the CS before writing: CSVALID=1 (bit 6 in GPMC_CONFIG7)?

Yes of course. I also implemented the configurations as menu scripts, so I can change configuration on the fly.
However, when I use the "synchronous" configuration, I can see the GPMC_CLK being enabled (which is to be expected), but the GPMC_AD lines remain at the same value (either 0 or as in the pictures below at the value of the MSB address word) during the first and second address phases - data (in case of write access) is output correctly though.

This is the complete GEL file script (as far as it regards GPMC configuration):

/* GPMC */

menuitem "GPMC"

#define FPGA_GPMC_CS                2

FPGA_GPMC_Config()
{
    GEL_TextOut("FPGA GPMC configuration is in progress ....... \n","Output",1,1,1);
    FPGA_GPMC_Config_PinMux();
    FPGA_GPMC_Config_Register_Asynchronous();
    GEL_TextOut("FPGA GPMC configuration is done \n","Output",1,1,1);
}

hotmenu FPGA_GPMC_Config_PinMux()
{
    GEL_TextOut("FPGA GPMC PinMux configuration is in progress ....... \n","Output",1,1,1);

    WR_MEM_32(CONF_GPMC_CSn0,    0x20);    // CSn0
    WR_MEM_32(CONF_GPMC_CSn1,    0x21);    // CLK
    WR_MEM_32(CONF_GPMC_CSn2,    0x20);    // CSn2

    WR_MEM_32(CONF_GPMC_WEn,    0x20);    // WEn
    WR_MEM_32(CONF_GPMC_OEn_REn,    0x20);    // OEn_REn
    WR_MEM_32(CONF_GPMC_ADVn_ALE,    0x20);    // ADVn_ALE

    WR_MEM_32(CONF_GPMC_AD0,    0x20);    // AD0
    WR_MEM_32(CONF_GPMC_AD1,    0x20);    // AD1
    WR_MEM_32(CONF_GPMC_AD2,    0x20);    // AD2
    WR_MEM_32(CONF_GPMC_AD3,    0x20);    // AD3
    WR_MEM_32(CONF_GPMC_AD4,    0x20);    // AD4
    WR_MEM_32(CONF_GPMC_AD5,    0x20);    // AD5
    WR_MEM_32(CONF_GPMC_AD6,    0x20);    // AD6
    WR_MEM_32(CONF_GPMC_AD7,    0x20);    // AD7
    WR_MEM_32(CONF_GPMC_AD8,    0x20);    // AD8
    WR_MEM_32(CONF_GPMC_AD9,    0x20);    // AD9
    WR_MEM_32(CONF_GPMC_AD10,    0x20);    // AD10
    WR_MEM_32(CONF_GPMC_AD11,    0x20);    // AD11
    WR_MEM_32(CONF_GPMC_AD12,    0x20);    // AD12
    WR_MEM_32(CONF_GPMC_AD13,    0x20);    // AD13
    WR_MEM_32(CONF_GPMC_AD14,    0x20);    // AD14
    WR_MEM_32(CONF_GPMC_AD15,    0x20);    // AD15
    
    GEL_TextOut("FPGA GPMC PinMux configuration done \n","Output",1,1,1);
}

hotmenu FPGA_GPMC_Config_Register_Asynchronous()
{
    UWORD32 temp;
    
    GEL_TextOut("FPGA GPMC Register configuration (asynchronous) is in progress ....... \n","Output",1,1,1);
    
    // Clear CSVALID
    temp = RD_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS));
    temp = temp & ~(1 << 6);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), temp);
    
    // AM339x GPMC Config Registers
    WR_MEM_32(GPMC_CONFIG1(FPGA_GPMC_CS), 0x00001100);
    WR_MEM_32(GPMC_CONFIG2(FPGA_GPMC_CS), 0x00060A00);
    WR_MEM_32(GPMC_CONFIG3(FPGA_GPMC_CS), 0x11030302);
    WR_MEM_32(GPMC_CONFIG4(FPGA_GPMC_CS), 0x05044804);
    WR_MEM_32(GPMC_CONFIG5(FPGA_GPMC_CS), 0x0008060A);
    WR_MEM_32(GPMC_CONFIG6(FPGA_GPMC_CS), 0x06040000);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), 0x00000010);
    
    // Set CSVALID
    temp = RD_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS));
    temp = temp | (1 << 6);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), temp);
    
    GEL_TextOut("FPGA GPMC Register configuration (asynchronous) done \n","Output",1,1,1);
}

hotmenu FPGA_GPMC_Config_Register_Synchronous()
{
    UWORD32 temp;
    
    GEL_TextOut("FPGA GPMC Register configuration (synchronous) is in progress ....... \n","Output",1,1,1);
    
    // Clear CSVALID
    temp = RD_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS));
    temp = temp & ~(1 << 6);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), temp);
    
    // AM339x GPMC Config Registers
    WR_MEM_32(GPMC_CONFIG1(FPGA_GPMC_CS), 0x28001100);
    WR_MEM_32(GPMC_CONFIG2(FPGA_GPMC_CS), 0x00060A00);
    WR_MEM_32(GPMC_CONFIG3(FPGA_GPMC_CS), 0x11030302);
    WR_MEM_32(GPMC_CONFIG4(FPGA_GPMC_CS), 0x05044804);
    WR_MEM_32(GPMC_CONFIG5(FPGA_GPMC_CS), 0x0008060A);
    WR_MEM_32(GPMC_CONFIG6(FPGA_GPMC_CS), 0x06040000);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), 0x00000010);
    
    // Set CSVALID
    temp = RD_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS));
    temp = temp | (1 << 6);
    WR_MEM_32(GPMC_CONFIG7(FPGA_GPMC_CS), temp);
    
    GEL_TextOut("FPGA GPMC Register configuration (synchronous) done \n","Output",1,1,1);
}

This is an asynchronous access to address 0x12345678 (16-bit address of the device: 0x011A2B3C):

And this is the same access to address 0x12345678 (16-bit address of the device: 0x011A2B3C) when the synchronous bits are set:

(In this case the LSB address word remains at the same value as the MSB address word).

Unfortunately, I never received any proper help from TI with this matter, neither could I find a "real" solution on my own - I decided to use the asynchronous mode instead (as a workaround as I was running out of time):
I'm sampling the incoming signals with 200 MHz within the FPGA, which worked for me (as the GPMC clock isn't always running, I did that already anyways).
I also managed to implement multiple read (burst / page read). Only downside is, I can't implement multiple write (burst write) access that way.

In case You find a solution, I would be glad if You share it with me. I'll probably try to investigate this matter when I've got some spare time, as multiple write access would decrease the data transfer time from DSP to FPGA alot.

Kind regards,
~ Felix