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C5509A Emif ARDY effect on the DSP and IRQ

Pierre-Alain Conus
Prodigy 20 points

Hello,


I would like to know the effect of ARDY pin on the execution of the code in the C5509A DSP ?

Does the code execution is blocked by hardware when ardy is low ? (which means that it is the DSP itself  which is blocked?)

What about the irq when ARDY is stuck at zero and CPU is blocked ?

Best Regards,

Pierre-Alain

  • 0
    TI__Genius 12575 points

    Hi,

    I think the same question is being asked through TI FAE. Below is the response (captured from the other thread).

    The ARDY pin on the EMIF is not meant to be used by a peripheral to support transfer stalls. The EMIF is meant to access memory and the ARDY pin is geared towards asynchronous memory. The HOLD/HOLDA mechanism is in place for a shared memory device and the ARDY pin prevents access to the EMIF in a case where the memory is not ready to be read/written to. Even if you used the DMA to service this peripheral, if the CPU needed to use the EMIF it would be held off because the ARDY pin would indicate that the interface is not ready. Note that the ARDY pin can be ignored by setting the ARDY off bit (see the EMIF User's Guide SPRU670A page 2-11).  One idea is to put this data in memory and send the C55x CPU an interrupt when that data is ready. This could be accomplished in a few ways. Does the data need to be parallel? If so what about using the HPI and putting the data in internal memory. This data could be moved from HPI to memory via the DMA. You could have shared memory space or a dual port memory and signal the C55x when it is ready. This is interupt driven not ARDY driven. The C55x CPU or DMA can get the data. Can the data be serial? So using a serial interface like a serial port that can be serviced by the DMA and moved into internal memory.

    Regards

     Vasanth