CPU Interrupts in MCBSP

Dear all,

I opened this  thread  https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/393966 . I try to setup the MCBSP interrupts in the evmC6657 following the instructions that the wiki provided. I use the function CpIntc_postSysInt for testing my configuration. Unfortunately, n o interrupt is generated.

You can find below the piece fo the code that I have written 

static T_Int32 const CICO_RX[CPU_CORES][PCM_MAX_LINES] =
{
	/// CIC0_OUT(4+20*n)
    /// CIC0_OUT(5+20*n)
	/// n is the core number
	{
		4,
		5,
	},
	{
		24,
		25
	}
};

static T_Int32 const  RINT_Event[PCM_MAX_LINES]        =
{
	32,
	36
};

static T_Int32 const CICO_TX[CPU_CORES][PCM_MAX_LINES] =
{
	/// CIC0_OUT(6+20*n)
	/// CIC0_OUT(7+20*n)
	{
		6,
		7,
	},
	{
		26,
		27
	}
};

static T_Int32 const XINT_Event[PCM_MAX_LINES]        =
{
	33,
	37
};

static T_Int8 const RINT_ids [2] =
{
		10,
		11
};
static T_Int8 const XINT_ids [2] =
{
		12,
		13
};

Void  initMCSBInterrupts(T_Int32 core_id)
{
	static UInt32 cookie = 0;
	Hwi_Params xparams;
	Hwi_Params rcvparams;
	int line =0 ;
	/* Disabling the global interrupts */
	cookie = Hwi_disable();
	//############################################################################
	//NOTE: Reference table 7.33 TMS320C6655/57
	// MCBSP
	for (line = 0; line < 2; ++line)
	{
	// transmit
		CpIntc_mapSysIntToHostInt(0, XINT_Event[line], CICO_TX[core_id][line]);
		/// Configures a CpIntc ISR dispatch entry
		CpIntc_dispatchPlug(XINT_Event[line],(CpIntc_FuncPtr) &PCM_hwHwiFxn, line, TRUE);
		///Enables the host interrupt
		CpIntc_enableHostInt(0, CICO_TX[core_id][line]);
		// Enable the System Interrupt
		CpIntc_enableSysInt(0, XINT_Event[line]);
		pcmHwLines[line].tx_event = CpIntc_getEventId(CICO_TX[core_id][line]);
		Hwi_Params_init(&xparams);
		xparams.arg 		  	  = line;
		/// required to be the host interrupt #
		xparams.eventId 	      = pcmHwLines[line].tx_event;
		xparams.enableInt 	      = TRUE;
		Hwi_create(XINT_ids[line], &CpIntc_dispatch, &xparams, NULL);
		// create ISR to handle this event in Hwi vector 10 + line
		Hwi_enableInterrupt(XINT_ids[line]);

		// receive
		CpIntc_mapSysIntToHostInt(0, RINT_Event[line], CICO_RX[core_id][line]);
		/// Configures a CpIntc ISR dispatch entry
		CpIntc_dispatchPlug(RINT_Event[line],(CpIntc_FuncPtr) &PCM_hwHwiFxn, line, TRUE);
		///Enables the host interrupt
		CpIntc_enableHostInt(0, CICO_RX[core_id][line]);
		// Enable the System Interrupt
		CpIntc_enableSysInt(0, RINT_Event[line]);
		pcmHwLines[line].rx_event = CpIntc_getEventId(CICO_RX[core_id][line]);
		Hwi_Params_init(&rcvparams);
		rcvparams.arg 		      = line;
		/// required to be the host interrupt #
		rcvparams.eventId 	      = pcmHwLines[line].rx_event;
		rcvparams.enableInt      = TRUE;
		Hwi_create(RINT_ids[line], &CpIntc_dispatch, &rcvparams, NULL);
		// create ISR to handle this event in Hwi vector 11 + line
		Hwi_enableInterrupt(RINT_ids[line]);
	}
	 CpIntc_enableAllHostInts(0);
	/* Restore interrupts */
	Hwi_restore(cookie);
	CpIntc_postSysInt(0,XINT_Event[0]);
	CpIntc_postSysInt(0,RINT_Event[0]);
	CpIntc_postSysInt(0,XINT_Event[1]);
	CpIntc_postSysInt(0,RINT_Event[1]);

}

Could you please mention to us  what is wrong?

Best regards

George