DM6446 DDR2 Controller Configuration for MT47H64M16HR-3

Please try using the config in this gel file and see if it makes any difference.

http://c6000.spectrumdigital.com/davincievm/revd/files/DaVinciEVM_arm.gel

Do you have CCS available/

Hi Paul,

Thanks for your reply.

I am using CCS 3.3 and have tried using the values in the gel file which comes with the CCS 3.3 installation and still my problem presists.

The values in the gel file given by you is based on 135MHz. But my target DDR2 should run at 162MHz.(which is the max possible on DM6446).

Anyway, i would let you know the status after testing with the values in the gel file given by you. 

What are the DDR2 specifications(DDR2-400,DDR2-533,DDR2-667 etc) supported by DDR2 Controller of DM6446? If i have to run my DDR2 part at 162MHz, which specification i should follow?

Sorry. I mean that gel file inside the package.

Just to confirm, you have tried the gel file in the package that's currently on spectrum digital website right? and your particular DDR is not working?

Your DDR2 part DOES work at 135MHz right?

DM6446 does support 162MHz DDR2

The only other document I can find is Implementing DDR2 PCB Layout on the TMS320DM644x DMSoC (Rev. G).

and http://www.ti.com/litv/pdf/sprue22c

I will let our DDR expert comment on this.

Hi Paul,

I have tried the gel file which comes with CCS3.3. It is configured for 162Mhz. My system hangs in this setup.

But My system works without hangs using the gel file you have provided in one of your previous mails.

ie, http://c6000.spectrumdigital.com/davincievm/revd/files/DaVinciEVM_arm.gel

In the above gel file, DDR2 controller is configured for 135MHz. So the observation is that my DDR2 is working only at lower frequencies.

Hi

Please try this

http://c6000.spectrumdigital.com/davincievm/revf/files/davincievm_arm.gel

I just verified this on our EVM

Hi Paul,

Unfortunately the DDR2 controller register values in the DVEVM Rev.F gel file (given in your previous mail) is also not solving my problem. My board is still hanging in between when my application runs.

Will it be something related to the Micron DDR2 SDRAM Die Revision? I am using MT47H64M16HR-3 IT:H. My application is working fine on a board assembled with MT47H64M16HR-3 IT:E. So the only change is the Die Revision from E to H. I have contacted spectrum digital for the information on what revision of SDRAm they use in their latest DM6446 DVEVMs. The answer was Rev.G of the same part above which is in between E and H. So spectrum digital has not started using Rev.H of the above micron part.

Has anyone faced similar application hang issues with using MT47H64M16HR-3 IT:H part in your boards? The part works fine under 135MHz, but causes instability at when operated at 162MHz.

Regards

Shiras

It may be related to the layout? Please make sure you meet our DDR layout guideline in the datasheet and the appnote 100%.

Also, maybe you should check with Micron on the exact difference between these two revisions (whether you should program it differently).

Hi Paul,

But I have been using MT47H64M16HR-37E IT:E and MT47H64M16HR-3 IT:E previously on the same board layout and these were working fine. Now that these parts are obsolete, i am forced to move to MT47H64M16HR-3 IT:H on the same board layout. The board layout has not changed across the different revisions of the DDR2 part. As per the DDR2 data sheet, there are no changes in AC timing operating specifications between all the above three parts. I have confirmed this with Micron also.So as per the DM6446 DDR2 controller datasheet, the values to be configured to the DDR2 controller registers also remain unchanged across the above 3 Micron parts.

I see.

I am trying to compare the ":H" timing in the Micron datasheet http://download.micron.com/pdf/datasheets/dram/ddr2/1GbDDR2.pdf

against our internal spreadsheet. This might take some time though. (I am using the timing from the -3E/-3 column, please check with Micron and see whether that's the right way).

As far as I see from the datasheet, -37E and -3 part have different timings.  So you need to verify that on your side.

It's not clear whether -3: E and -3:H have identical timings. So you need to ask Micron to really verify their timings are identical

In the mean time, please have a look at this http://www.ti.com/litv/pdf/spraac5g, and do make sure follow everything suggested there.

Hi Paul,

You have to take the values under -3 column in Table 11 of the DDR2 datasheet, for the timings for MT47H64M16HR-3 IT:H. -3E is a different speed grade and so taking its values would create wrong timings for the part MT47H64M16HR-3 IT:H.

The AC timing operating specifications which affect DM6446 DDR2 controller register configurations are tRFC,tRP,tRCD,tWR,tRAS,tRC,tRRD,tWTR,tXSNR,tXSRD,tRTP and tCKE. All these timings are same for both -37E and -3 parts.You may find some other timings different between these parts.But, those are not affecting the DDR2 controller register settings.So in short, both -37E and -3 should work with the same DDR2 register settings and this is observed in my case.The only difference is between -3 IT:E and -3 IT:H, which differ only in Die revisions.For Die revison changes, the above timings doesnt change as per data sheet. As per micron, the only change will be Die Size,when they move to a new revision.The timings should be the same across revisions of the same speed grade.

Currently, i have configured DDRDRIVE bit to 1(Weak drive strength, which is the default settings). Do you think changing it to "Normal drive strength" would help?

Also, i will have a check of my board layout against spraac5g.

Paul,

I believe I have the exact same problem except I see I see it at cold temperatures (-10 to -20C).   Uboot will just hang.  I'm running at 162Mhz DDR clock freq too.  My new boards changed the same Micron DDR2 memory from revision E to revision H.  (MT47H64M16HR-3 IT).  Did you come up with a solution to this problem?

thanks,

Russ Wood

Yes, I solved the problem by reducing the series termination resistance value of the differential clock lines from the Davinci DDR2 interface to the DDR2 Chip, from 47 ohms to 22 ohms.

Hi!Paul,

               I met the same trouble,

此前我们使用三星的K4T1G164QQ-HCF7（DDR-800），在我们初期的开发板上，有6套正常工作，由于没有就行阻抗控制，我们怀疑另外3片DDR2不工作是阻抗失配，对他们切片测试分析发现的确有这个问题；
             然后我们对第二批板就行阻抗控制在50-55欧姆之间，结果发现使用K4T1G164QQ-HCF7的板加大时钟CLK+，CLK-上串联端接的电阻并且在两时钟线上分别并联22pf电容到地，则DDR2可以正常工作，而使用K4T1G164QF-BCF7的板必须将时钟CLK+，CLK-上串行端接电阻改为50cm长的导线后DDR2可以工作正常，使用K4T1G164QQ-HCF7的板使用串线的办法同样可以使DDR2正常工作；我们怀疑是串扰等原因，因此让深圳汉普电子公司重新帮我们Layout这个PCB文件。
              但是重新用汉普提供的PCB文件生产10片主板后发现，现象没有消失，这两种不正常的DDR2问题表现的是，如果通过CCS解析*.gel文件写DDR2区域，1K数据总是有几个字节是错误的，即使主频降频到48MHz也是如此，我们曾经尝试使用MT47H64M16-37E（DDR2-533），H5PS1G63EFR-S6（DDR2-800）发现数据完全错误。您是否可以帮我们分析一下为什么串50cm长的线可以正常呢？为什么加大串行端接的电阻并且并联电容DDR2可以正常呢？我们怎样修改才可以消除这个问题呢？