• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 1078 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

McBSP(I2S format) channel reversal problem.

masataka suto
Prodigy 130 points
Other Parts Discussed in Thread: TMS320C6748

Hello,

Problem with McBSP and EDMA3.
Channel reversal is occurred about once in five times.
Data corresponding to FSX/FSR is reversed as seen in the pictures below.

Transfer format is I2S(32bit, 2ch).
EDMA3 is used to transfer data between McBSP and buffer.
I initialize McBSP according to Technical Reference Manual.
("TMS320C6748 DSP Technical Reference Manual　24.2.12 McBSP Initialization Procedure")

I need to switch sampling rate(44.1kHz, 48kHz, 88.2kHz, etc.).
McBSP is stopped before each switching.
Sampling rate switching is processed as shown below.
Channel reversal is occurred after starting McBSP.
* stop McBSP and EDMA3
* switch frequency of CLKS
* start McBSP and EDMA3 according Technical Reference Manual.

Once McBSP and EDMA are started correctly, channel reversal is not occurred until the modules are stopped.
This problem appears in both TX and RX.
FIFO is not related with this problem.

I tried the method written in "TMS320C6748 DSP Technical Reference Manual　24.2.12.2 Special Case: External Device is the Transmit Frame Master" and "processors.wiki.ti.com/index.php", but the problem is not resolved.

I would like to resolve this problem.

Thanks.

  • 0
    Mastermind 6115 points
    Hi Masakata,

    Welcome to E2E Forum. Thanks for your post.

    Try to probe the CLKS. You need to confirm that clock is continues.
    I suspect clock synchronization can be the issue.
    Also try with internal McBSP clock , make yourself ensure that proper internal synchronization happens.

    If the external device provides the bit clock, wait for two CLKR or CLKX cycles. If the McBSP generates the bit clock as a clock master, wait for two CLKSRG cycles. In this case, the clock source to the sample rate generator (CLKSRG) is selected by the CLKSM bit in SRGR and the SCLKME bit in PCR.

    Please follow each step as mentioned in Technical Reference manual.
    section 24.2.12.1 (General Initialization Procedure)

    Also probe SRGR (Sample Rate Generator Register) and check if you feel any weird behaviour.
  • 0
    Mastermind 6115 points
    Hi Masataka,

    Is your issue resolved?
  • 0 in reply to Arvind Singh
    Prodigy 130 points
    Hi Arvind,

    Thanks for your reply and I'm sorry for the delay.

    The problem in TX seems to be resolved by waiting 2 clock cycles,
    but the channel reversal in RX is still not resolved.

    My clock source setting is below.
    * The McBSP generates CLKX and CLKFSX.
    * The external device provides CLKR and CLKFSR.

    The waiting time is required to be exactly 2 clock cycles?
    Is there any other point to check when the receiver is used?

    Best regards,
    Masataka Suto.