AM3352 power-up sequence

Nomo

Other Parts Discussed in Thread: AM3352

Hello,

Please let me know the following sequence invokes the problem.

- In case of the Figure 6-3 of the datasheet, VDDS_RTS is supplied to AM3352.
- Next, PMC_POWER_EN goes to high, and RTC_PWRONRSTn is released.
- After RTS_PWRONRSTn is released, the IO power rails such as VDDSHV1 are supplied.
- And then, however, PMIC is in trouble, IO power goes to 0V.
- Finally, VDDS_RTC is supplied, PMIC_POWER_EN is High, and RTC_PWRONRSTn is High (reset is released).

I want to know whether the condition of which VDDS_RTC is supplied, PMIC_POWER_EN is High, and RTC_PWRONRSTn is High is allowed.

Best Regards,

Nomoto

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Nomoto-san,

As you say this is a PMIC failure situation. This is not a power-up sequence, only the RTC power domain remains powered in this situation, so if all other supplies are off and PORz is low there shouldn't be any damage to the processor.

0 Nomo over 10 years ago in reply to Biser Gatchev-XID

Guru 16800 points

Hello Biser-san,

Thank you for your reply, and I apologize to miss the words.
This is a PMIC failure situation.

Best Regards,

Nomoto

Processors

Processors forum

AM3352 power-up sequence