Speeding up the serial SPI Boot Load?

One thing to note is that the bootloader will run at 6 MHz unless you make a change.  Your firmware settings that select the x15 clock multiplier for 90 MHz are not in place until after the bootloader is done and your firmware has started running.

I suggest that you write some test firmware which runs in the debugger (no bootloader needed) to determine the maximum safe clock speed for your SPI memory device.  Once you have confirmed the maximum speed that your boot memory can handle, then you can proceed to try making the bootloader run faster.

On my hardware, I have a 66 MHz ATMEL Flash memory, a 12 MHz external crystal, and internal clock of 108 MHz.  My firmware testing proved that I could run the SPI at 54 MHz safely.

The bootloader documentation warns against altering the MCBSP clock generator during the bootloader, but I tried it and it works fine.  You have the option of changing the internal clock only, to get to 90 MHz instead of only 6 MHz.  You might also experiment with bumping up the MCBSP clock generator, but that could be a risky choice considering the documentation.  However, if it works, I don't see why it would change in the field.

I'm using 0x1c00, 0x2492 and 0x280b, 0x0102 for a TMS320VC5506 running at the maximum of 108 MHz, and SPI running at 54 MHz.  That's boosting the bootloader speed by about 1,098 times.  Your register settings look fine at first glance, but you might have better luck if you test the SPI connection with the EEPROM before expecting the bootloader to work.

Thanks for the reply Brian.

I'm particularly encouraged to hear you have this working at far higher speeds than I require so I am far happier to pursue it.  The test firmware is a also good idea that I had not considered.

Regards and thanks for the advice, Andrew.

I started a discussion titled "SPI bootloader settings for McBSP0 on C5506" back in September, but it seems to have expired from the E2E forum.  That's a shame, because Brad Griffis was telling me that the information should be helpful to archive since the 5503/5506/5507/5509A won't have any new revs. So I'll just summarize what I discovered back then.

It's fairly easy to discover the settings that are used by the SPI bootloader. Just open the McBSP0 register window in the debugger, reset the processor, and then step forward. You will have to wade through the code that sets up and reads the GPIO pins.  It's also a good way to learn C55x assembly.  Here are the McBSP0 registers that are changed, the rest are left at their default reset values as documented in the manual:

SPCR1_CLKSTP_DELAY

SPCR2_FREE_YES

RCR2_RDATDLY_1BIT

XCR2_XDATDLY_1BIT

SRGR1_FWID=1, _CLKGDV=243

PCR_FSXM_INTERNAL, _CLKXM_OUTPUT, _FSXP_ACTIVELOW, _FSRP_ACTIVELOW, _CLKRP_RISING

These bootloader settings run the SPI at 49.4 kHz with a 12 MHz crystal and only 24.7 kHz with your 6 MHz clock.  That's painfully slow, but safe for all hardware.

I decided to compare our CLKMD settings. Obviously, you're setting PLL MULT to 15 while I have to use 9 or less with my 12 MHz crystal. But I also note that you're setting BREAKLN to 0 where I set it to 1. Technically, this is a Read-only bit, so it should make no difference, but I thought it might be worth noting.

Your Hex55 options should bump the SPI up to 737.7 kHz, if only it worked.

Another difference is that I do not have any -delay options at all. Perhaps that's why your bootload fails?