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Where does Timer12 get its clock? (OMAP-L138)

Walter Snafu
Genius 3450 points
Other Parts Discussed in Thread: OMAP-L138, OMAPL138

The Starterware software uses "Timer12", but, in the OMAP-L138, where does Timer12 get its clock? The OMAP-L138 TRF makes no mention of Timer12.  I am trying to get an internal clock to Timer 12.  But no clock so far. 

Tedious details of confusion:

I am confused about how Starterware software clocks the OMAP-L138 timers.  My confusion arises from the various conflicting names used when the TRF refers to the timers (spruh77a.pdf).

The TRF shows Timers0/1 getting clock AUXCLK, and Timers2/3 getting clock ASYNC3, (figure 7-1), but nowhere else does the TRF even mention "Timers0/1" or "Timers2/3".  The TRF does mention Timer64P0/P1 and Timer64P2/P3. ???  The TRF also mentions timer0, timer1, timer2, timer3 exactly once each, (concerning emulation suspend), which (mistakenly?) suggests there are four timers on the chip, not just two timers.  

In some places the TRF refers to "timer 1:2" and "timer 3:4" (but what does the colon mean?  Isn't timer12 a single-entity; a single timer?  Or is it two timers?)  And again, where do these get their clocks?

Perhaps this confusion arises partly from porting the Starterware software over from the Stellaris chips. 

Thank you for your help.

-- Walter Snafu

  • 0
    TI__Mastermind 43955 points

    Hi Walter Snafu,

    In OMAPL138, there are four 64 bit general purpose timers. Out of four, all the four can be configured as two 32 bit General purpose timer.

    They are,

    • Timer64P0,
    • Timer64P1,
    • Timer64P2
    • Timer64P3

    In the clocking diagram

            --> Timer 0 and TImer 1 are nothing but the Timer64P0 and Timer64P1.They get the clock from the AUXCLK.

            --> Timers 2 and Timer 3 are nothing but the Timer64P2 and Timer64P3. They get the clock from the SYSCLK2.

    In some places the TRF refers to "timer 1:2" and "timer 3:4" (but what does the colon mean?  Isn't timer12 a single-entity; a single timer?  Or is it two timers?)  And again, where do these get their clocks?

    There are actually two modes of timer configurations. One is 64 bit mode and the other is Dual 32 bit timer mode. In the dual 32 bit timer mode, there are two types. They are chained mode and unchained mode.

    Dual 32 bit timer mode:

    To represent the dual 32 bit timer mode, the first 32 bit timer is represented as timer1:2 and the second 32 bit timer is represented as timer3:4.

    64 bit mode:

    In 64 bit mode, you will not see the indication "timer1:2" or "timer3:4"; because it is one single 64 bit timer.

    The Starterware software uses "Timer12", but, in the OMAP-L138, where does Timer12 get its clock? The OMAP-L138 TRF makes no mention of Timer12.  I am trying to get an internal clock to Timer 12.  But no clock so far. 

    TIM12 and TIM34 are the timer counter registers. It is a common acronym used for all the four timers (Timer64P0,Timer64P1,Timer64P2, Timer64P3) .

    i.e., The memory mapped address for this TIM12 register for the four timers are given below.

    ----------------

    In the starterware, these are the macro values which hold the value of the period which needs to be set for the timers.

    #define TMR_TIMER12                        (0x00003FFEu)
    #define TMR_TIMER34                        (0x3FFE0000u)

    Regards,

    Shankari

    ------------------------------------------------------------------------------------------------------------------------------

    Please click the verify answer button on this post if it answers your question.

    ------------------------------------------------------------------------------------------------------------------------------

  • 0 in reply to Shankari G
    Genius 3450 points

    Shankari G,

    Thank you for your helpful, thorough, and clear answer.  (I will click the verify button, ... as soon as I can find it.......)

    Your Table-6-131 is also helpful.  [Though I cannot find it in either of my TRFs, (spruh77a.pdf and sprs586d.pdf). The data in that table does correspond to data scattered throughout the memory map given in sprs586d.pdf.] 

    -- Walter Snafu

  • 0 in reply to Walter Snafu
    TI__Mastermind 43955 points

    Hi Walter,

    Glad to hear that it clarifies and thanks for verfying the answer.

    The Table 6-131 is given at page no: 255 in the data sheet of OMAPL138 :

    Regards,

    Shankari