We have a PCIe device that does DMA reads from 8168 DDR. The PCIe device has to be set to do 2 outstanding transactions to maintain the required throughput. Unfortunately the PCIe device treats read completions out of order as a DMA error and data gets lost. Normally the device issues two 64 word reads in a row and the 8168 completes them in order with two 32 word transacations. Due to the frame format there is a shorter read at the end of the frame that sometimes completes before the previous full-size transaction.
To solve this we have been able to pad the frame to prevent the short read which prevents the out of order completions. We have a new feature requirement that is not compatible with the padded frame size thus we are looking for another solution for this. Is there anything that can be done or we can try on the 8168 PCIe settings to make the read completions happen in order?