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Using GPMC Registers to access Externel Device

Other Parts Discussed in Thread: CCSTUDIO

Hi ,

 We are using DM 8148 EVM. We are making a custom board and planning to Access FPGA from processor using GPMC. Now from TRM I am unable to understand how to access GPMC registers clearly. Should we access our FPGA using NAND COMMAND, NAND DATA,NAND ADDRESS registers present in GPMC Register set. Can you please provide some pointers to start working on it ? What should be the Timing values in Config registers to access FPGA ? 

Regards,

K.Pranay

  • Hi Pranay,

    kashetty pranay kumar said:
    Can you please provide some pointers to start working on it ?

    See if the below pointers will be in help:

    kashetty pranay kumar said:
    What should be the Timing values in Config registers to access FPGA ?

    This depends on your external device/FPGA and use case.

    kashetty pranay kumar said:
    Should we access our FPGA using NAND COMMAND, NAND DATA,NAND ADDRESS registers present in GPMC Register set.

    I do not think so, these looks to be NAND specific.


    Regards,
    Pavel

  • Hi Pavel,

    Thank you for the links. I will go through the links provided. Meanwhile if the NAND COMMAND.,NAND ADDRESS,NAND DATA registers should not be used to access FPGA, what registers should I use ?? There are no other registers in TRM in GPMC which are used to exchange data between GPMC and externel memory device. 

    Thank you,

    K.Pranay kumar

  • Pranay,

    It is possible to consider accessing FPGA as a NAND-like memory interface, though I believe that is rarely used. In this case the GPMC address bits are unused and the registers GPMC_NAND_COMMAND_i, GPMC_NAND_ADDRESS_i, GPMC_NAND_DATA_i, can be used to communicate with the external device.

    See the below links for more info regarding accessing external device without using these 3 registers:

    e2e.ti.com/.../148547
    e2e.ti.com/.../311898
    e2e.ti.com/.../320844

    Regards,
    Pavel
  • Hi Pavel,

    Thanks for the reference links. From the  link   I understood that NOR flash is also like a part of Processor memory. We can directly access the NOR flash using memory read/write utility. The starting address of the NOR flash will be my base address of the chip select. Here my doubt is the NOR flash requires commands to be given( like read,write,erase,buffer etc). These commands are series of predefined data writes on the data bus (as per NOR data sheet). So how these commands are given if we simply write in to the NOR location( base address of Chip select ) directly. Is my understanding of accessing NOR flash is correct ??

    If correct how to manage these commands for writing to NOR flash ?? 

  • Pranay,

    See the below links for how to access NOR flash:

    processors.wiki.ti.com/.../TI81XX_PSP_UBOOT_User_Guide
    processors.wiki.ti.com/.../TI81XX_PSP_NOR_Driver_User_Guide
    processors.wiki.ti.com/.../TI81XX_PSP_04.04.00.02_Feature_Performance_Guide

    See also the CCStudio project available from the Mistral web page:

    NOR_Flash/

    This CCS test application validates the NOR-Flash for its ability to perform write access read access and data storing ability. The test application first erases the sectors to be written, writes a known pattern into the desired number of sectors and then reads back the same.
    If the data read does not match the expected pattern, this test is declared failed. It is declared pass otherwise.

    Regards,
    Pavel