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PCIe Advisory Non-Fatal Error issue when AHCI controller(88SE9182A) writes to SATA SSD on K2E EVM

Guohu Xu38
Prodigy 240 points

Hi Experts,


I'm writing the PCIe controller driver on K2E EVM for an RTOS.
I use the onboard 88SE9182A PCIe-to-SATA AHCI chip for verifying the PCIe driver.

Currently, I face such situation: The SATA SSD can be identified and read by our AHCI driver. The identify and read can work in both legacy INTx and MSI mode. But when written, the 88SE9182A never responds to PCIe controller with interrupt, neither legacy INTx nor MSI.

When displaying the PCI status for both RC and 88SE9182A, I find "Advisory Non-Fatal Error" in  RC, and Received Master-Abort (RMA) flag in 88SE9182A. This 2 error conditions only occur after write operation.

I suspected that the inbound mapping didn't work, so I map the PCIe address 0x80000000 to CPU address 0x80000000, with size of 2GB, but it doesn't help.

I disable the BAR0 and BAR1 for RC in Linux, the read/write operate normally. So it shouldn't be the inbound mapping issue.

I also suspected there was issue in AHCI driver, so I used other Marvell AHCI(88SE9128) PCIe card to verify on other boards, the read/write operation is fine. So I think the AHCI driver is no problem.

I tried many other configuration changes to the PCIe controller, but no effect.

I can't find any way to go ahead.

Could anyone give any suggestion, please? Thank you!


Best Regards,

Guohu

  • 0
    TI__Mastermind 28085 points
    Hi,

    Please provide your EVM revision information, older version EVM required hardware changes for PCIe port1 (PCIE-to-SATA).
    e2e.ti.com/.../1289661

    Have you configured the K2E EVM as RC on your setup? Please provide more information about your setup. What is the EP on your setup?

    Have you using MCSDK PCIe example for your testing?

    Thanks,
  • 0 in reply to Ganapathi Dhandapani95
    Prodigy 240 points
    Hi Ganapathi,

    Thanks for the quick respond!

    I got the new version of the K2E board on which the PCIe port 1 has been fixed. The link training can come to up. I don't remember the detail version, and the board is not on my hand now. I'll update it tomorrow.

    Yes, I've set the PCIe port 1 to RC mode(set register 0x0262014c, Bit[4:3] to 0b10). The EP in my scenario is 88SE9182A, it's an AHCI controller, and the same AHCI driver can work for 88SE9128 card on other board.

    Since I can't find a SATA example in MCSDK, and I don't have a backboard for connecting 2 K2E EVM to testing the pcie_example case, I haven't run it yet.

    Following are PCIe Controller settings:
    App Regs: 0x000
    4e321100 00000007 00010000 00000000
    00000000 00010000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000003 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000001 00000001
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    60000001 00000000 60800001 00000000
    61000001 00000000 61800001 00000000
    62000001 00000000 62800001 00000000
    63000001 00000000 63800001 00000000
    64000001 00000000 64800001 00000000
    65000001 00000000 65800001 00000000
    66000001 00000000 66800001 00000000
    67000001 00000000 67800001 00000000
    68000001 00000000 68800001 00000000
    69000001 00000000 69800001 00000000
    6a000001 00000000 6a800001 00000000
    6b000001 00000000 6b800001 00000000
    6c000001 00000000 6c800001 00000000
    6d000001 00000000 6d800001 00000000
    6e000001 00000000 6e800001 00000000
    6f000001 00000000 6f800001 00000000
    00000001 80000000 00000000 80000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000
    Type1 Regs: 0x1000
    8888104c 00100007 06040001 00010010
    21020000 80000008 00010100 00000000
    60006000 0001fff1 00000000 00000000
    00000000 00000040 00000000 00000100
    Logic Regs: 0x1700
    00c00040 ffffffff 07000004 1b0f6400
    00030120 00000000 000103aa 00000500
    00000000 00000003 034f5811 08000410
    80c: 0000020f
    capabilities:
    PM Cap
    00035001 00000000
    MSI Cap
    00807005 00000000 00000000 00000000
    PCIe Cap
    00420010 00008001 0009281e 00133422
    30220048 00000040 004003c0 00000000
    00000000 0000001f 00000000 00000006
    00000002
    PCIe Ext Cap
    00010001 00000000 00000000 00062030
    00002000 00002000 000001e0 00000000
    00000000 00000000 00000000 00000000
    00000000 00000000


    Thanks,
    Best Regards,
    Guohu
  • 0 in reply to Guohu Xu38
    Prodigy 240 points

    Hi,

    This problem is solved by setting the Maximum Read Request Size to 256 in the EP.

    Thank you for helping on this!

    Regards,

    Guohu

  • 0 in reply to Guohu Xu38
    TI__Mastermind 28085 points
    Thanks for your update. It will help for other community members.