ARM to ARM interrupt with CHIPSIG

Hi Ibrahim,

Could you please tell me what are trying to do.
Do you want write any ISR routine for any occurrence via hw or sw ?

The code seems to be linux driver, so we can write a driver for GPIO interrupt which is very easy to trigger any interrupts and executing the ISR calls.

Also, please elaborate a bit on your requirement.

Actually I am trying to test shared memory. At the beginning, i write to share memory , then send interrupt CHIPSIG2 from ARM to DSP .
Upon receiving the interrupt, the DSP will write to share memory and reply with interrupt CHIPSIG1.

On the ARM side, after receiving the CHIPSIG1 interrupt, will react by printing a message on the console
printk(KERN_ALERT "*** Ping Back CBAD to ARM after sending DCBA to DSP ***\n");

But somehow, this message does not appear. That is why, i test in case The ARM interrupt ARM again.

I register the ISR in the .tcf file

bios.HWI.instance("HWI_INT5").useDispatcher =1;
bios.HWI.instance("HWI_INT5").interruptSelectNumber =5;
bios.HWI.instance("HWI_INT5").interruptMask = "all";
bios.HWI.instance("HWI_INT5").fxn=prog.extern("handleIRQTest22");
// 5 is SYSCFG CHIPSIG Register CHIPINT2 Interrupt

and have the checking in handleIRQTest22

# define SHARED_MEM_PHY_ADDR_BASE 0xC70FFF70
# define ARM_TO_DSP_SIDE_INFO_BUFFER_SIZE 128 // bytes
# define SYS_BASE 0x01C14000
# define SICR *(unsigned int*) (0xFFFEE024)
# define CHIPSIG *(unsigned int*)(SYS_BASE + 0x174)
# define CHIPSIG_CLR *(unsigned int*)(SYS_BASE + 0x178)

define SYSCFG_CHIPSIG_CHIPSIG4 (0x00000010u)
#define SYSCFG_CHIPSIG_CHIPSIG3 (0x00000008u)
#define SYSCFG_CHIPSIG_CHIPSIG2 (0x00000004u)
#define SYSCFG_CHIPSIG_CHIPSIG1 (0x00000002u)
#define SYSCFG_CHIPSIG_CHIPSIG0 (0x00000001u)
#define SYSCFG_CHIPINT2 5


void handleIRQTest22( )
{
u2* cmdBuf;

u2 cmdLength;
/* We disable the interrupt until we are done with this message: */
HWI_disable();

CHIPSIG_CLR |= SYSCFG_CHIPSIG_CHIPSIG2;//0x0004;
SICR &= 0;
SICR |=SYSCFG_CHIPINT2;//5;

cmdBuf = (u2*) (SHARED_MEM_PHY_ADDR_BASE);

if((cmdBuf[0] & 0xFFFF) == 0xDCBA)
{

cmdBuf[3]=0xCBAD;
CHIPSIG |= SYSCFG_CHIPSIG_CHIPSIG3;
}


HWI_enable();

}

Meanwhile on the ARM side

# define DSP_TO_ARM_DATA_IRQ 31
# define CHIPSIG_CLR 0x01C14178
# define SICR 0xFFFEE024
# define SYSCFG_CHIPSIG_CHIPSIG2 0x00000004u
# define SYSCFG_CHIPSIG_CHIPSIG3 0x00000008u
# define CHIPSIG_CLR_DATA_IRQ3 0x00000008
# define SHARED_MEM_PHY_ADDR_BASE 0xC70FFF70

for interrupting the DSP


/********************************************************************************************************************************/
// Ping DSP
/********************************************************************************************************************************/
u16* cmdBuf;
u32* chipsigReg;

cmdBuf = (u16 *) ioremap(SHARED_MEM_PHY_ADDR,128);
chipsigReg = (u32 *) ioremap_nocache(CHIPSIG,sizeof(u32));

printk(KERN_ALERT "*** Pinging The DSP ***\n");

iowrite16(0xDCBA,cmdBuf);
iowrite32(SYSCFG_CHIPSIG_CHIPSIG2,chipsigReg);


/********************************************************************************************************************************/







// Registration of the ISR upon receiving CHIPSIG3 interrupt
ret = request_irq(DSP_TO_ARM_DATA_IRQ,
(void*)&dataDsptoArm_isr,
IRQF_DISABLED,
"dsp2ArmISR",
dev);

irqreturn_t dataDsptoArm_isr(int irq, void *dev_id, struct pt_regs * regs)
{

int i;
u16 attributes;
u16* buffer;
u32* chipsigClear;
u32* sicr;

printk(KERN_ALERT "****Receiving Packet from DSP****\n");
/*
* Write a 1 to the CHIPINT1 bit of the Chip Signal Clear (CHIPSIG_CLR)
* register, then write the IRQ to the System Interrupt Status Index Clear
* (SICR) register to clear the interrupt.
*/
chipsigClear = (u32 *) ioremap_nocache(CHIPSIG_CLR,sizeof(u32));
sicr = (u32 *) ioremap_nocache(SICR,sizeof(u32));
buffer = (u16 *) ioremap(SHARED_MEM_PHY_ADDR_BASE ,128);

iowrite32(CHIPSIG_CLR_DATA_IRQ3,chipsigClear);
iowrite32(irq,sicr);

// Checking The Rx Buffer

attributes = ioread16( (u16*)(buffer + 3));
if(attributes == 0xCBAD)
{
printk(KERN_ALERT "*** Ping Back CBAD to ARM after sending DCBA to DSP ***\n");
break;
}

}