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C6748 EMIFA [0]

Guillaume DEHAYES59
Prodigy 30 points

Hi all,


I use a SDRAM on the EMIFA [0] and all register are configured.

But when I try access at SDRAM with the mode DEBUG (i use gel file), I have this message :

"Verification failed: Values at address 0x40000000 do not match. Please verify target memory and memory map"
 and when I look the signal CS[0] is always at 1.

Is it normal? if not, how manage it please?

thanks

Guims

  • 0
    TI__Guru* 84110 points

    Guillaume,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages. Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics.

    What are you referring to with DEBUG mode? I find no mention of that in the TRM. Your reference may help with understanding your situation.

    With EMA_CS[0] staying at 1 all the time, you are definitely not accessing the SDRAM. Please try reading from other EMIFA CS spaces to see if any of them work on your board.

    Are you using a TI-supported EVM or is this a custom board of your design?

    Are you looking at EMA_CS[0] at the C6748 pin/pad or at the SDRAM pin/pad? Please look at the C6748 or as close as possible to it.

    Regards,
    RandyP

  • 0
    TI__Guru** 116100 points

    Hi Guims,


    "Verification failed: Values at address 0x40000000 do not match. Please verify target memory and memory map"

    This errors seems to be from CCS console when you tried to access the memory.

    How did you get this error i.e what you have done to get this error ?
    Tried to access the memory through CCS's memory browser ?
    Or got this error when you do connect target (while loading gel file ) ?


    Have you modified the gel file for SDRAM at EMIFA,CS[0] ?
    If not, modify the SDRAM timing registers in gel file & do "connect target" on CCS and try to access the SDRAM memory through CCS's
    memory browser.


    "Verification failed: Values at address 0x40000000 do not match. Please verify target memory and memory map"
    and when I look the signal CS[0] is always at 1.


    It (CS) must be low and address lines should toggle when you access the memory.

    If you are running any code, then please make sure that you have modified PINMUX registers for EMIFA & CS pin selection.

  • 0 in reply to Titusrathinaraj Stalin
    Prodigy 30 points

    Hi Titus,

    Thanks for your reply


    I get this error when I do connect target while loading gel file.

    Titusrathinaraj Stalin said:
    Have you modified the gel file for SDRAM at EMIFA,CS[0] ?
    If not, modify the SDRAM timing registers in gel file & do "connect target" on CCS and try to access the SDRAM memory through CCS's
    memory browser.


    Yes, I modified the gel file and PINMUX for SDRAM at EMIFA[0]

    Regards,

    Guims

  • 0 in reply to RandyP
    Prodigy 30 points

    Hi RandyP,

    RandyP said:
    What are you referring to with DEBUG mode? I find no mention of that in the TRM. Your reference may help with understanding your situation.

    I refers to CCS DEBUG for the DEBUG mode

    RandyP said:
    Are you using a TI-supported EVM or is this a custom board of your design?

    I use a custom board of my design. And on the EMA_CS[0] between the C6748 and the SDRAM, I put a Pull-up resistor on this signal.

    RandyP said:
    Are you looking at EMA_CS[0] at the C6748 pin/pad or at the SDRAM pin/pad?

    I look at EMA_CS[0] at the C6748 pin/pad

    Regards,
    Guims