Am335x LCD Controller

user611719

Hi,

Am335x LCDC transfers frame data from DDR2 RAM to its internal FIFO buffer by DMA all the time if raster mode has already started.

Thus one question, can I change LCDDMA_FBx_BASE or LCDDMA_FBx_CEILING register when transferring frame data, anytime?

It means, a sample shows me that the timing which LCDDMA_FBx_BASE or LCDDMA_FBx_CEILING register are changed is at the raster end of frame interruption.

What happens If changing LCDDMA_FBx_BASE or LCDDMA_FBx_CEILING register asynchronously regardless of the interruption? The LCD screen will be sometimes corrupted?

Regards.

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi,

After an EOF0 or EOF1 interrupt, it takes a certain latency (L) before the ISR can set cfg_fb0_base, cfg_fb0_ceil, cfg_fb1_base, and cfg_fb1_ceil. Meanwhile, the DMA uses the current values of those registers for the next frame immediately after firing the interrupt.

L = 10 cycles of the L3 or L4 clocks (whichever is slower).

0 user611719 over 10 years ago in reply to Biser Gatchev-XID

Prodigy 70 points

That's it!
I modified the timing at which cfg_fb0_xxxx registers are set. . to avoid the critical timing like above. Then the display corruption was improved!

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Am335x LCD Controller