[DM3730] About Suspend Mode Issue after setting DDR Frequency from 200MHz to 166MHz

Hi Yimin,

The problem is not known and I have need of some details to investigate the issue. Could you share which SDK and kernel version you are using? Could you describe what do you do to change the frequency?

BR
Tsvetolin Shulev

Hi Sir

1. We modified the DDR frequency in dpll3_init_36xx() function 

   platform.S

core_36x_dpll_param:
.word 200, 12, 0, 1
.word 200, 12, 0, 1
.word 200, 12, 0, 1
.word 166, 12, 0, 1 // 200 

2. The sdk version is Android GINGERBREAD 2.3 - Dev Kit for DM37x (Kernel v2.6.32  )

if you want more detailed information, please let us know.

Thanks in advance.

Hi Yimin,

The changes which you have made are not enough to guarantee the stable work of the system. You should check the memory chips manufacture and modify its SDRC timings in the ../x-loader/include/asm/arch-omap3/mem.h to be appropriate for 166 MHz frequency.

BR

Tsvetolin Shulev

Hi Sir

1. We have done DDR timing adjustment to be appropriate for 166 MHz frequency.
2. Do you have any suggestion for log message ? it seems some Powerdomains cannot go into state 0 entirely.

BR
Yimin

Hi Yimin,

I successfully reproduce the issue and found it is due to some dependencies between processor's subsystems clocks and memory clock which could be seen at fig 10-47 of DM3730 TRM. I found in the kernel that some dependencies are broken in your case because the kernel needs to re-initiate the DDR clock (for 166 MHz) for proper operating of the system.

BR
Tsvetolin Shulev

Hi Sir

Thanks for your reply.

Do you have any document or tips how to re-initiate the DDR clock (for 166 MHz) in kernel ?

I have no idea and needs more suggestion from you.

BR
Yimin

Cvetolin,

Did you see the problem while switching to 166Mhz not being able to suspend always or occasionally? 

Did it crash? This case we are encountering is system can still go to suspend but IVA is not able to enter retention occasionally so power consumption is high when it is not enter retention. 

Why the change (DPLL3) from 200Mhz to 166Mhz affect the IVA(use DPLL2)? 

You mentioned about re-initiate DDR clock, it seems more about resume, not suspend.

Any input is welcome. 

BR, Rich

Yimin,

The re-initialization of the DDR clock is set in a header file which depends on the DDR memory chips manufacture. For the referent board dm3730evm which I'm using the DDR memory is Hynix H8KDS0UN0MER-4EM and the header file is ../kernel/arch/arm/mach-omap2/sdram-hynix-h8kds0un0mer-4em.h which is included in the board file (board-omap3evm.c) in my case. To determine your DDR memory see the first parameter of the "omap2_init_common_devices(h8kds0un0mer4em_sdrc_params, NULL);" function in the board file.

The structure which describes the DDR settings is something like:

static struct omap_sdrc_params h8kds0un0mer4em_sdrc_params[] = {
    [0] = {
        .rate        = 200000000,
        .actim_ctrla = 0x92e1c4c6,
        .actim_ctrlb = 0x0002111c,
        .rfr_ctrl    = 0x0005e601,
        .mr          = 0x00000032,
    },
   

where you should change the .rate to 166000000 but you should check the datasheet of your DDR memory for the other settings.

BR

Tsvetolin Shulev

Rich,
There is no settings for 166 MHz in the DDR header file (Hynix H8KDS0UN0MER-4EM) which my board (dm3730evm) using. Therefore I think it is not very correct to test the behavior of my system with DDR clocked at 166 MHz.

BR
Tsvetolin Shulev

Hi, Tsvetolin,

The EVM you use run with DRAM capable to operate to 200Mhz which means it can operate in lower clock than 200Mhz. Set our controller to 166Mhz with corresponding parameter setting then it can operate at 166Mhz always.

Moreover, this issue is more about IVA and some other domains can not enter retention but not system cannot wake up. Re-initial DDR memory could be a direction but how do you see the IVA power domain issue while switching to 166Mhz.

Did you see crash or system cannot enter suspend while switching DPLL3 from 200 to 166?

Best Regard,
Rich

Rich,
When I try to configure the DDR to operate to 166 MHz in the kernel the system stuck during kernel booting. This behavior is due to missing information about timings about 166 MHz for Hynix h8kds0un0mer memory. The omap_sdrc_params structure in the sdram-hynix-h8kds0un0mer-4em.h header file has timing data only for 100 MHz and 200 MHz. I added timing settings for 166 MHz which works properly with similar DDR memories but not with this one. There are some examples:
.rate = 166000000,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,
or
.rate = 165941176,
.actim_ctrla = 0x9a9db4c6,
.actim_ctrlb = 0x00011217,
.rfr_ctrl = 0x0004dc01,
.mr = 0x00000032,

The DDR initialization which Yimin makes in the x-loader only but not int the kernel is not correct and may causes unexpected behavior and I suppose that the issue about IVA and some other domains can not enter retention could be caused of this initialization.

BR
Tsvetolin Shulev