Customer is interfacing DM6437 McBSP to Micron N25Q00AA serial flash. They have the McBSP configured as SPI master and can read and write to the nonvolatile registers on the Micron chip. The problem is that the Micron chip requires a longer frame width than 32 bits when programming or reading- a single programming operation requires the command (1 byte), the address (4 bytes), and the data to be programmed (more bytes!). The frame sync pulses that are generated automatically each time a packet is transmitted (32 bit packet width) are interpreted by the Micron chip as canceling the operation. My understanding from the McBSP User’s Guide (SPRU943C) is that this configuration is required for McBSP SPI-master configuration (page 54):
The McBSP can also provide a slave-enable (SS) signal on the FSX pin. If a slave-enable signal is required, the FSX pin must be configured as an output, and the transmitter must be configured so that a frame-sync pulse is generated automatically each time a packet is transmitted (FSGM = 0). The polarity of the FSX pin is programmable high or low; however, in most cases the pin should be configured active-low.
When the McBSP is configured as described for SPI-master operation, the bit fields for frame-sync pulse width (FWID) and frame-sync period (FPER) are overridden, and custom frame-sync waveforms are not allowed. The signal becomes active before the first bit of a packet transfer, and remains active until the last bit of the packet is transferred. After the packet transfer is complete, the FSX signal returns to the inactive state.
Are there any workarounds that would allow custom frame widths while in McBSP SPI-master configuration? What driver needs to be modified to make this happen?
Please advise.
Thanks,
Mark
