Dear all,
I try to configure two EDMA controllers fro the C6657 platform . The one should handle the interrupts from MCBSP and the other should make QDMA transfers. But when the interrupt is called , either from the EDMA 0 or EDMA 1, the instance of the one edma is always used. It depends on the value of the ccXferCompInt[0][0].
Something should be wrong in the way that I have registered the interrupts in each of these EDMA instances.
Please find below the piece of the code that do the interrupts registration
unsigned int ccXferHostInt[2][2] = {
{0u, 20u},
{2u, 22u}
};
//CIC0_OUT(1+20*n)
//CIC0_OUT(3+20*n)
unsigned int edma3ErrHostInt[2][2] = {
{1u, 21u},
{3u, 23u}
};
unsigned int ccXferCompInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_REGIONS] = {
{
24u, 25u, 26u, 27u,
28u, 29u, 30u, 31u,
},
{
24u, 25u, 26u, 27u,
28u, 29u, 30u, 31u,
}
};
/**
* Variable which will be used internally for referring channel controller's
* error interrupt.
*/
unsigned int ccErrorInt[NUM_EDMA3_INSTANCES] = {16u, 16u};
/**
* Variable which will be used internally for referring transfer controllers'
* error interrupts.
*/
unsigned int tcErrorInt[NUM_EDMA3_INSTANCES][EDMA3_MAX_TC] = {
{
18u, 19u, 20u, 21u,
0u, 0u, 0u, 0u,
},
{
18u, 19u, 20u, 21u,
0u, 0u, 0u, 0u
}
};
EDMA3_DRV_GblConfigParams sampleEdma3GblCfgParams[NUM_EDMA3_INSTANCES] =
{
{
/* EDMA3 INSTANCE# 0 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
64u,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
8u,
/** Total number of TCCs supported by the EDMA3 Controller */
64u,
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
512u,
/** Total number of Event Queues in the EDMA3 Controller */
4u,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
4u,
/** Number of Regions on this EDMA3 controller */
8u,
/**
* \brief Channel mapping existence
* A value of 0 (No channel mapping) implies that there is fixed association
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
1u,
/** Existence of memory protection feature */
1u,
/** Global Register Region of CC Registers */
(void *)0x02740000u,
/** Transfer Controller (TC) Registers */
{
(void *)0x02790000u,
(void *)0x02798000u,
(void *)0x027A0000u,
(void *)0x027A8000u,
(void *)NULL,
(void *)NULL,
(void *)NULL,
(void *)NULL
},
/** Interrupt no. for Transfer Completion */
24u,
/** Interrupt no. for CC Error */
16u,
/** Interrupt no. for TCs Error */
{
18u,
19u,
20u,
21u,
0u,
0u,
0u,
0u,
},
/**
* \brief EDMA3 TC priority setting
*
* User can program the priority of the Event Queues
* at a system-wide level. This means that the user can set the
* priority of an IO initiated by either of the TCs (Transfer Controllers)
* relative to IO initiated by the other bus masters on the
* device (ARM, DSP, USB, etc)
*/
{
0u,
1u,
2u,
3u,
0u,
0u,
0u,
0u
},
/**
* \brief To Configure the Threshold level of number of events
* that can be queued up in the Event queues. EDMA3CC error register
* (CCERR) will indicate whether or not at any instant of time the
* number of events queued up in any of the event queues exceeds
* or equals the threshold/watermark value that is set
* in the queue watermark threshold register (QWMTHRA).
*/
{
16u,
16u,
16u,
16u,
0u,
0u,
0u,
0u
},
/**
* \brief To Configure the Default Burst Size (DBS) of TCs.
* An optimally-sized command is defined by the transfer controller
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
{
64u,
64u,
64u,
64u,
0u,
0u,
0u,
0u
},
/**
* \brief Mapping from each DMA channel to a Parameter RAM set,
* if it exists, otherwise of no use.
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
* \brief Mapping from each DMA channel to a TCC. This specific
* TCC code will be returned when the transfer is completed
* on the mapped channel.
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
* \brief Mapping of DMA channels to Hardware Events from
* various peripherals, which use EDMA for data transfer.
* All channels need not be mapped, some can be free also.
*/
{
0xFFFFFFFFu,
0xFFFFFFFFu
}
},
{
/* EDMA3 INSTANCE# 0 */
/** Total number of DMA Channels supported by the EDMA3 Controller */
64u,
/** Total number of QDMA Channels supported by the EDMA3 Controller */
8u,
/** Total number of TCCs supported by the EDMA3 Controller */
64u,
/** Total number of PaRAM Sets supported by the EDMA3 Controller */
512u,
/** Total number of Event Queues in the EDMA3 Controller */
4u,
/** Total number of Transfer Controllers (TCs) in the EDMA3 Controller */
4u,
/** Number of Regions on this EDMA3 controller */
8u,
/**
* \brief Channel mapping existence
* A value of 0 (No channel mapping) implies that there is fixed association
* for a channel number to a parameter entry number or, in other words,
* PaRAM entry n corresponds to channel n.
*/
1u,
/** Existence of memory protection feature */
1u,
/** Global Register Region of CC Registers */
(void *)0x02740000u,
/** Transfer Controller (TC) Registers */
{
(void *)0x02790000u,
(void *)0x02798000u,
(void *)0x027A0000u,
(void *)0x027A8000u,
(void *)NULL,
(void *)NULL,
(void *)NULL,
(void *)NULL
},
/** Interrupt no. for Transfer Completion */
25u,
/** Interrupt no. for CC Error */
16u,
/** Interrupt no. for TCs Error */
{
18u,
19u,
20u,
21u,
0u,
0u,
0u,
0u,
},
/**
* \brief EDMA3 TC priority setting
*
* User can program the priority of the Event Queues
* at a system-wide level. This means that the user can set the
* priority of an IO initiated by either of the TCs (Transfer Controllers)
* relative to IO initiated by the other bus masters on the
* device (ARM, DSP, USB, etc)
*/
{
0u,
1u,
2u,
3u,
0u,
0u,
0u,
0u
},
/**
* \brief To Configure the Threshold level of number of events
* that can be queued up in the Event queues. EDMA3CC error register
* (CCERR) will indicate whether or not at any instant of time the
* number of events queued up in any of the event queues exceeds
* or equals the threshold/watermark value that is set
* in the queue watermark threshold register (QWMTHRA).
*/
{
16u,
16u,
16u,
16u,
0u,
0u,
0u,
0u
},
/**
* \brief To Configure the Default Burst Size (DBS) of TCs.
* An optimally-sized command is defined by the transfer controller
* default burst size (DBS). Different TCs can have different
* DBS values. It is defined in Bytes.
*/
{
64u,
64u,
64u,
64u,
0u,
0u,
0u,
0u
},
/**
* \brief Mapping from each DMA channel to a Parameter RAM set,
* if it exists, otherwise of no use.
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
40u, 41u, 42u, 43u, 44u, 45u, 46u, 47u,
48u, 49u, 50u, 51u, 52u, 53u, 54u, 55u,
56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
* \brief Mapping from each DMA channel to a TCC. This specific
* TCC code will be returned when the transfer is completed
* on the mapped channel.
*/
{
0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u,
8u, 9u, 10u, 11u, 12u, 13u, 14u, 15u,
16u, 17u, 18u, 19u, 20u, 21u, 22u, 23u,
24u, 25u, 26u, 27u, 28u, 29u, 30u, 31u,
32u, 33u, 34u, 35u, 36u, 37u, 38u, 39u,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP, EDMA3_RM_CH_NO_TCC_MAP,
56u, 57u, 58u, 59u, 60u, 61u, 62u, 63u
},
/**
* \brief Mapping of DMA channels to Hardware Events from
* various peripherals, which use EDMA for data transfer.
* All channels need not be mapped, some can be free also.
*/
{
0xFFFFFFFFu,
0xFFFFFFFFu
}
}
};
Could you please help to find a solution?
