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DDR3 Write Address Problem using SRIO in 66AK2H14

bjkong
Prodigy 180 points
Other Parts Discussed in Thread: 66AK2H14

hi, everyone!

I want to send data directly to an external DDR3 memory using SRIO

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my system :

xilinx virtex7 fpga <===== SRIO =====> 66AK2H14

66AK2H14 DDR3 : 2Gbyte in DDR3B(0x80000000 ~ 0xFFFFFFFF)

                               0x60000000 ~ 0x7FFFFFF : aliased 0x80000000 ~ 0x9FFFFFFF

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1. FPGA ==> DSP (NWRITE)

    : Destination Address(0x70000000 ~ 0x7FFFFFFF)

      ==> work very well

2. FPGA ==> DSP (NWRITE)

      : Destination Address(0x90000000 ~ 0x9FFFFFFF)

      ==> Do not write

             srio port error state : "input retry stoped" state(SPn_ERR_STATE Register : 0x00000002 -> 0x00000402)

DDR3 Access using CCS is not problem..

What is Problem?

please help me...

best regards.

   

  • 0
    TI__Mastermind 43955 points

    Hi bjkong,

    You have to look into the *.cfg file ( open it with text editor in CCS) in which the DDR3B memory space will be allotted.

    For example:

    heapMemParams.size = 0x8000000;

    For example, in one of the cfg files, the shared DRAM is alloted something like below:

    /* Shared Memory base address and length */
    var SHAREDMEM           = 0x0c200000;
    var SHAREDMEMSIZE       = 0x00200000;

    Regards,

    Shankari

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