Hello
I am afraid I am back with another UART question (interrupt mode, fifos enabled). When receiving and sending at the same time (i.e. both interrupt sources enabled), I see lots of RXFIFOE interrupts when the FIFO is seemingly empty:
- The IIR indicates RXFIFOE as the cause of the interrupt
- The LSR also has RXFIFOE set, and sometimes BI and FE (yes, I am receiving breaks), but has DR = 0 which I though indicates that there is no data to read.
My question is: How do I properly react to this condition? What state is that anyway? How can the data in RBR be erroneous if RBR is empty? Normally, I would treat RXFIFOE very much like DR, so I would read all characters from the FIFO, dealing with any errors (FE, BI, PE) as they occur. I would expect DR to become 0 eventually, at which point all error flags would have been cleared. But given that DR=0 indicates that the FIFO is empty, what can I do? Right now, I am stuck in a RXFIFOE interrupt, because I cannot properly clear it and IIR will always report RXFIFOE whatever I do.
Also, what happens if I read RBR despite DR=0? The PSP driver will sometimes happily do that, but I wonder if it could lead to problems or if it could hang.
My fallback plan is to disable the RXFIFOE interrupt, which seems to work well, but will lead to unnecessary latency with how I want to use the UART (yes, I am planning to send a break after a message, so RXFIFOE will occur roughly three characters before the timeout interrupt I would otherwise have to use).
Thanks a lot
Markus
