C674x uPP WAIT Signal in Receive Mode

Titus,

Thank you for your reply.

I'm still doubt that the WAIT pin of uPP in the receive mode, will be asserted when processor is busy.
In the TRM of C674x, there are not timing charts which show WAIT assertion in the receive mode.
And the descriptions of the UPICR.WAITA and UPICR.WAITB register fields says:
"Only applied when Channel A/B is configured in transmit mode using the MODE bit in the uPP channel control register (UPCTL). In receive mode, WAIT is always driven low."

If the WAIT will be asserted as you said, I'm interested in if under-run caused by DMA reprogramming miss, when DSP is too busy to handle the DMA ISR, will assert the WAIT.

Best regards,
Tsutomu Furuse

TI DSP experts,

Would you please give me further information on the above question?

Best regards,
Tsutomu Furuse

Titus,

Thank you for the clarification.

Best regards,
Tsutomu Furuse