I have a custom board, that I am able to successfully boot my Code Image from NAND into internal memory (MSMCRAM & L2SRAM). I am using the NON I2C boot option.
I have verified I can emulate the same program in DDR3 after re-configuring my RTSC platform module, using the gel file file to configure the peripherals, and loading the program.
How do I go about adding the boot configuration table to my code image (that I load into the processor) to enable the DDR3 prior to the RBL downloading the code to DDR?
The SPRUGY5C "KeyStone Architecture DSP Bootloader User Guide" describes (on page 23) using this Boot Configuration Table to do exactly this ( configure DDR to download code with the Boot Configuration Table). However, I have not been able to dig up how to add this into the file I burn into the flash.
I am following the NandWriter process cited in some of the other posts on this forum:
https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/p/335996/1177713
https://e2e.ti.com/support/dsp/c6000_multi-core_dsps/f/639/t/329841
It may be as simple as adding it to somewhere (before or after the boot table) in the ascii .dat file I load into memory, but I have not seen any information about where the boot configuration table goes.
Also the boot configruation table is supposed to be 3 elements (per the DSP bootloader User Guide)...are these 3 32 bit values?
Thanks,
Mark
