Hi
I am using SDk 7 and AM3352. I am facing an issue with MCSPI driver. We only use the second SPI master( from TRM we understand AM335x provides 2 master's and 2 chip selects per each master ).
use case: In addition to the spidev driver utilizing the SPI node Spidev2.1( initialized via linux device tree ), we also have our own custom driver which makes use of SPI 2.0. i.e. SPI master 2 and chip select 0.
As far as I understood, the McSPI driver is configured as a single channel master. Following is the sequence and what works and what does not:
1) Verify spidev nodes correctly initialized at bootup. Use an application to read/write on the spidev2.1 node. Everything works fine as seen from the scope( both MISO/MOSI lines indicate data ).
2) Load our custom driver ( after which driver creates a new device object for master 2 and chip select 0 ). Also verified the MCSPI_CH0CONF was again being written for new node as base address of SPI controller is different for chip select 0 and 1. ( In case this helps, base address being used for master 2 and chip select 0 and 1 are: 4196008192 and 4196008212 respectively ( in decimal ) ).
3) Here the custom driver works correctly and we can verifiy that MISO/MOSI lines do transmit/receive data. Next we unload the custom driver.
4) Use an application to utilize spidev2.1 to read/write data. This does not work. We can only transmit data( MOSI has data) but not receive data ( MISO remains in default state ). We verified that on unloading the custom driver and utilizing our application the chip select 1 base address was utilized to re-configure MCSPI_CH0CONF. All read/write now seems to be happening on master 2 and chip select 1.
As far as I can understand, the above should work as we use only one channel at a time and re-configure the channel when we switch between various chip selects.
Please do let me know your thoughts and if I am doing something which is fundamentally flawed. I have never worked on SPI earlier.
Regards
Manbir
