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dMAX and SPI slave on C7627 DSP

RenêBenvenuti
Prodigy 40 points

Hi,

 

I'm trying to configure SPI slave with dMax.

For slow transfers (rates up to ~1.5Mbps), there is no problem, but, when I set bus SPI speed for 4Mbps ++, the SPI slave (C6727) seems to not be able to output data in time.

For example, in the picture below, I set to transfer 0xFFFF data in 16 bits frame format, but the C6727 could not output the data correctly. Sometimes the master read 0x7FFF from the bus.

 

 

 

I’m using the following setup:

Spi:

Slave mode; polarity 0 (inactive low); phase 1; length 16

dMax:

SPI priority low; eSize 16bits; polarity falling edge

 

Thank you all,

Renê Benvenuti

  • 0
    TI__Mastermind 43660 points

    Hello,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    Have you verified all your hardware connections and PCB routing is proper ?

    Are you always missing the MSB or random missing ?

    Regards,
    Senthil

  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 40 points

    Hi Senthil,

    I'm getting random mismatches, and they do not always occur in the MSB.

    I've tried to increase the clock frequency using PLL to 300MHz (was 240MHz before), and it helped, but not solved the issue. Now I’m wondering if this delay in SOMI data could be caused by some clock issue or dMax misconfiguration.

    Regards,

    Renê

  • 0 in reply to RenêBenvenuti
    TI__Mastermind 43660 points
    Hello Rene,

    When you are changing the device frequency, how it helped you ? Could you please explain more on that ?

    I would suggest you to ensure the dMax configuration is correct. Also check the clock requirements are met.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 40 points
    Hello Senthil,

    Changing the device frequency, I got a little improvement on SPI->MISO timing. The data was output faster and the misread occurred not so often.

    I’m seeking for dMax configuration issue…. Nothing found so far.

    Some update are that I could not get SPI working when using phase=0 on C672x, and, reading the datasheet errata for 1.2 silicon revision, I’ve found that phase=1 should not be used.

    Regards,

    Renê
  • 0 in reply to RenêBenvenuti
    Prodigy 40 points
    Hello,

    Reading the "spru_795d.pdf", I've found that dMax uses 84 cycles to transfer data from SRAM to SPI peripheral.

    Please correct me if I'm wrong, but considering that I was using PLL frequency of 228MHz and peripherals at 114MHz, dMax could use, in worst case, 84/114Mhz = ~737ns to transfer data to SPI, so the maximum SPI transfer rate will be ~1.357Mbps. I conclude that, when I speed up the transfer from ~1Mbps to 4Mbps I got many SPI transfer errors because dMax could not transfer data in appropriate rate.

    When I changed the PLL multiplier to 25 (300MHz), and peripherals 150Mhz, I have some improvement because 84/150M ~= 560ns, and then SPI max rate ~=1.8MHz.

    Is that right???

    Someone ever get dMax and SPI working at higher rates?

    Regards,
    Renê
  • 0 in reply to RenêBenvenuti
    TI__Mastermind 43660 points
    Hello Rene,

    That might be a cause for your SPI transfer error. The dMax SPI controller should be capable to transfer the data at the rate you desire. From the above statements, i guess there should be a limitation on the data transfer rate from the dMax.

    I don't think we have information on the successful C6727 SPI slave interface with dMax.

    Regards,
    Senthil