SRIO performances

Hi

For performance elaboration I used TSCx CPU regs like

    //Get CPU timer
    iTime = CSL_chipReadReg(TSCL);
    for (i=0; i < (iTest_Size >> (12-2)); i++) {
        srio_write(0x900000, 0xE0000000 + i*0x1000, 0x1000);
    }
    //Get CPU timer
    iTime = CSL_chipReadReg(TSCL) - iTime;
    fTime = (iTime*1.0E-9);
    printf("SRIO Write transfer %d KBytes with time %6.2fs @%6.2fMB/s\n", iTest_Size>>8, fTime, (iTest_Size >> 18)/fTime);

srio_write()  using LSUx engine (from DSK6455 example)

My results about 550 MB/s at 4X mode @2.5Gb/s for 128MB block (N_Write). Moreover, every 4K block (256Bx16) received by FPGA during ~6.4us, i.e.  625MB/s - this is probably maximum nwrite performance for 4X@2.5Gb/s for 6455.

BR, Serge

Hi Serge

thanks  for your advice.the question now is how can I adapt this library (TSC ) to compute clock cycle on EVLTMS320c6474?

do
 you have any code of 6474.

thanks

Hi, tarik

I suggest you should correct source of  SD's example project with sub-path evmc6474_v1\csl_C6474\example\srio\srio_evm_dio_example\build\

like that:

#include <csl_chip.h>

...

main()  {

...

CSL_chipWriteReg(TSCL, 0); //start TSCx count

...

iTime = CSL_chipReadReg(TSCL); //story CPU count at call func

srio_write( .... );

iTime = CSL_chipReadReg(TSCL) - iTime; //calculate CPU count during  func activity

fTime = (iTime*1.0E-9); //time in sec calculated as CPU tick * CPU tick period (1ns@1GHz)

Have a nice weekend,

Serge

Hi serge

thanks for your advice.when i done what you told me i have this error in compilation:

--------------------  Srio_evm_dio_exampleSrc.pjt - Debug  --------------------
[Srio_evm_dio_exampleSrc.c] "C:\CCStudio_v3.3\C6000\cgtools\bin\cl6x" -g -k -al -o3 -fr"../obj/Debug" -i"../../../../inc" -d"_DEBUG" -mo -ml3 -mv6400+ -@"../build/Debug.lkf" "Srio_evm_dio_exampleSrc.c"
"Srio_evm_dio_exampleSrc.c", line 195: error: identifier "TSCL" is undefined
1 error detected in the compilation of "Srio_evm_dio_exampleSrc.c".

>> Compilation failure

Build Complete,
  1 Errors, 0 Warnings, 0 Remarks.

in fact ,after some reserch i found that "TSCL" is a registre ,but it s undefined!!

do you have an idea about this prob?

Hi, tarik

There are some muddle with name of C64+ core registers in  CSL_ChipReg definition: for c6455 CSL they named without "CSL_CHIP_" prefix but

in others (e.g. C6474 CSL) there heve full name like CSL_CHIP_TSCL.

BR, Serge

Hello,

Is the compilation problem solved?... I am getting the same error even though i have included  #include "c6x.h"

Thanks!