TMS320C6748-Query

Hi Deelip

Deelip Sutar said:

(a) VDDARNWA, VDDARNW1 pins are mentioned. which DSP has these pins? Because those pins are not there in C6748.Please clarify on this?

VDDARNWA and VDDARNW1 are design names for the RVDD pins (Internal RAM supply pins). We will fix this on the webpage soon, to stay consistent with the datasheet terminology. Please make sure you pay attention to RVDD pins, and connect them to 1.2V (many customers miss out on connecting this to power at first blush).

Deelip Sutar said:

(b) For the similar pin group the current requirement is mentioned as 200mA in html page and 250mA in another pdf file(Application Report-slva340).What is exact curent requirement for TMS320C6748?Please clarify on this.

You can use 200 mA as shown on the webpage. We recently recommended this update to the power management team based on the silicon power char work we have. The slva340 does not reflect these updates yet.  Have you decided on the power management solution for your design?

Deelip Sutar said:

.If we are not using SATA and USB1 modules can we leave the SATA_VDD, SATA_VDDR and USB1_VDDA18, USB1_VDDA 33 pins unconnected?

The datasheet needs to be updated to show recommendations for SATA and USB1 when not used. For the time being,  I will point you to datasheets of other devices that belong to the same family and already have the datasheet updates. You can use that as a reference for now, till the c6748 datasheet gets updated. If you have any questions/concerns please let us know

For SATA pins , please refer to the AM1808 datasheet , Table 6-48 . NOTE if you are designing with PG1.x silicon make sure that SATA_VDD is connected to static 1.2V supply. PG2.0 onwards these pins can be left as NC too.

For USB1 pins, please refer to c6747 datasheet, Table 6-1.

Deelip Sutar said:

For DDR2SDRAM controller’s data (I/O) bus, one series termination at DDR2 module is shown in the datasheet high-level schematic in page no.106 of C6748. Please let us know whether one termination(at DDR2 side) is sufficient or whether series termination is required at both source(DSP ) and destination(DDR2) end?

Please refer to section 6.11.3.9 in the datasheet and let me know if this doesn't address your query

Deelip Sutar said:

Please let us know whether any excel sheet for power calculation of TMS320C6748 is available. 

An external/customer/product folder ready version of this spreadsheet would be available in a month or two (don't have exact dates yet). Meanwhile if you have any power related queries or issues, feel free to post them here or work with your TI support team.

Regards

Mukul

Hi Mukul

Thanks for your reply.

We have few queries regarding DDR2 controller and DDR2 termination.

1) In TMS320C6748 DDR2 controller, There is no DDRODT pin (as compared to DDR2 controller of TMS320C6474 which has DDRODT pin).Please let us know whether DDR2 controller of TMS320C6748 include any on-die terminating resistors?

2)It is mentioned in “TMS320C674x/OMAP-L1x Processor DDR2/mDDR Memory Controller User’s guide” that ODT pin of DDR2 SDRAM must be grounded(to disable on-die termination).In this case there is no on-die termination either at DDR2 controller  or at DDR2 SDRAM.

Also it is mentioned in section 6.11.3.9 of TMS320C6748 datasheet that “No terminations of any kind are required in order to meet signal integrity and overshoot requirements”. Please clarify on this.

Also, Please let us know whether external termination (series termination at both ends of bidirectional data bus of DDR2) is required if trace length is more?

Regards

Deelip

Hi Mukul

You have mentioned that for PG2.0 silicon onwards,SATA_VDD pin can be left as NC if we are not using SATA.

But in the ordering information(page 248 of datasheet) there is no option of silicon revision 2.0

Please let us know whether option "A" in the part number-TMS320C6748AZWT3 means Silicon revision 2.0?

Regards

Deelip

Please see page 2/3 of the errata:

http://www-s.ti.com/sc/techlit/sprz303b

A = rev 1.1

B = rev 2.0

Hi Deelip

From Mariana's post you should be able to figure out the nomenclature for rev1.x vs rev2.0.

If for whatever reason you are unsure of what devices you will order or you would be ordering a mix of rev1.x and rev2.0, then I recommend you trace out the SATA_VDD pins to 1.2V supply , and have the capability of making them NC once you have PG2.0 silicon available to design with for your production design.

Let us know if you have any additional questions/concerns.

Regards

Mukul

Mukul,

If DDR is not used then what is the required connection to its pins?

Regards   ---   Roger

Hi Roger

This is a relatively new query that has come up in context of these devices (typical queries are w.r.t to SATA and USB being un-used). 
Based on PRELIMINARY assessment and analysis , we think it is ok to leave them all as NC (Table below).

However, till this recommendation makes it to the datasheet or some formal TI collateral, I would recommend you to treat this as preliminary guidelines. I would also  recommend that ,if possible, you have unpopulated resistor pads in your preliminary design (assuming you cannot wait till the final recommendations are put in the TI collateral).

Let us know if you have any follow up questions or concerns.

Unused DDR2/mDDR Controller Signal Configuration

⁽¹⁾ To minimize power consumption, the DDR2/mDDR controller input receivers should be placed in power-down mode by setting VTPIO[14]=1.

Mukul,

Thanks for this. So not using SATA, USB, DDR, & using only 3.3V IO means I can get rid of the 1.8V regulator & assoc powerup/down stuff. Maybe I'll feed the 1.8V from a resistor divider off the 3.3V at least while this is not formally verified as true.

One more question along these lines. Which power regime is RESET- on? It says there is an internal pull up so the pull up is the where? (I need to drive RESET- with a totem pole output.)

Regards   ---   Roger

Hi Roger

roger littlewood said:

So not using SATA, USB, DDR, & using only 3.3V IO means I can get rid of the 1.8V regulator & assoc powerup/down stuff.

You will still need a 1.8V supply for DVDD18 power pins (even if you don't use SATA, USB and DDR). The dual-voltage IO buffers require 3 supplies: CVDD, a static 1.8V supply and the variable 1.8V or 3.3V supply.  DVDD18 is the static 1.8V supply to these pins.

roger littlewood said:

One more question along these lines. Which power regime is RESET- on? It says there is an internal pull up so the pull up is the where? (I need to drive RESET- with a totem pole output.)

All the dual IOs are divided into 3 power groups (A/B/C), each group can be individually configured to either as 1.8 or 3.3 V IOs.  nRESET is part of power group B. Since you plan to have all IOs run as 3.3 V IOs, this will be 3.3 V IO for you.

Regards

Mukul

Mukul,

Ah yes of course I forgot about DVDD18! In that case may as well connect 1.8V to SATA, USB, DDR anyway.

So now it seems the main reason for the 1.8V 3.3V sequencing requirement is really to keep the absolute difference between these rails always <2V (As discussed in this thread http://e2e.ti.com/support/dsp/tms320c6000_floating-point_dsps/f/115/t/43170.aspx) ?

In our application we have no voltage much higher than 1.2V available at start, so in this case we could kick off the 3.3V rail when 1.2V is good, and generate 1.8V from the 3.3V rail via an LDO series regulator, and with a reverse diode across the regulator. This would make the 1.8V track the 3.3V up to 1.8V, and also make the 1.8V collapse no faster than the 3.3V at power off no matter what the relative bulk capacitance and currents may be. Would this configuration meet the sequencing requirements?

Regards   ---   Roger

Hi Roger

Sorry for the delay in response. I am still taking a second opinion on this internally.
However on the face of it, I think what you are proposing will violate the power up sequencing requirement. It is required that the 1.8V supplies come up before 3.3V supply, which will not be met from what you describe.

Would it be possible for you to share a visual of your power supply sequencing and concept schematic (could be a block diagram).

Regards

Mukul

Hello Mukul,

Attached a concept block diagram. At power up the 3.3V will come up when 1.2V reaches 1V. The 1.8V will track the 3.3V but stop at 1.8V. When 3.3V reaches 2.7V the processor will be taken out of reset. At power down the rails could collapse in any order depending on bulk capacitance and actual current draw, in this circuit 1.2V is on its own. If 3.3V is above 1.8V the 1.8V rail will be at 1.8V. If 3.3V rail is below say 1.5V the 1.8V rail will track the 3.3V down. Thus 1.8V & 3.3V rails are never more than 1.5V apart, and at power up they track.

In this design we are very short of PCB area, so I'm trying not to add too many parts.Thanks for your help.

Regards --- Roger

Hi Roger

We are not able to download the attachment. Can you please repost. FYI some forum re-organization is going on right now, so I am not sure if the error is from your side, or a by product of the re-structuring.

Regards

Mukul

Hello Mukul,

You can find a copy here http://www.era5.co.uk/C6748/psu.pdf

Thanks   ---    Roger

Hi Roger

Thanks for re-posting the block diagram. I discussed this with the team, and I am afraid this is not going to meet the recommendations/guidelines set in place in the datasheet. The power-sequencing requirements mandates having the 1.8V supplies be powered on before the 3.3 V supplies in the system. The 2V difference between 1.8 and 3.3V supplies is more to do with the ramp requirements (not the power up sequence requirements).

I hope you are aware of the solutions put in place on www.ti.com/power , there is one with discrete LDOs (3.3V input)

http://focus.ti.com/lit/an/slva342/slva342.pdf

This might  not be as optimal from a board/bom constraint that you might be working with, but I just thought I'd post the link in case you hadn't seen it.

Regards

Mukul

Hello Mukul,

OK thanks for this information. I have seen the suggested solutions, but in this case we have no 3.3V or 1.8V initlally available, I'll have to power up the 3.3V DC-DC to power the 1.8V reg but disconnect its output from the C6748 with a fet while 1.8V comes up.

Thanks for your help   ---   Roger

Roger,

Mukul forwarded me your question.  I have seen your block diagram and believe I understand what you are trying to do.  Theoretically, since you are powering the 1.8V with a LDO and 3.3V with a DCDC, the 1.8V rail will power up instantly after the EN reaches its threshold voltage the device is turned on.  So, the 1.8V will reach regulation while the 3.3V is still ramping in softstart. 

However, to guarantee the turn-on of 1.8V prior to 3.3V, you are correct to use an inline FET on the 3.3V that is enabled by the 1.8V LDO output or from a PG output (if the LDO chosen has a PG output).

Let me know if you have any further questions.

Regards, Andy.

Andy,

According the the block diagram, when the 1.2V is OK the 3.3V rail will power up, the 1.8V rail is derived from the 3.3V so it will rise with the 3.3V until 3.3V reaches just above 1.8V, then the 3.3V will continue to go up to 3.3V.

I understand I'm pushing the specs a bit, so based on Mukul's last post I've made it follow the spec exactly, just now trying to figure out how to force it to follow the spec at power down in the worst case of rails collapsing...... without too many bits & pieces!

Regards   ---   Roger

hello

Am not sure where to post my query about accessing DSP  in omap 3530.In fact my project is brain computer interface with embedded system,but  after acquiring the signal how to dump it on omap and how to write a code is becoming a real difficulty. can u please guide me through this