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Question about timer_0 clock on C6748

jie wang75279
Intellectual 740 points

Hi engineers：

     We debugging C6748 with JTAG, Now we need to calculate the bandwidth(such as DDR),So we use timer0 as the timer counter.

    we use the  internal clock as the timer clock source,the datasheet said that"The internal clock source to the timer is generated by the PLL controller",But the problem is thart which one of PLL controller outputs is ?how we know what the value of the timer clock?

              That is say What is the logical relationship between CPU clock and timer clock? We hope you help!!

or can you tell us a better way to get the CPU running time to calculate the bandwidth?? Thanks very much!!

Best wishes!!

                                                                                                                                                                              lingling zhan

  • 0
    TI__Guru** 116100 points
    Hi,
    Please refer to the following TI wiki page for clock profiling.

    processors.wiki.ti.com/.../Profile_clock_in_CCS

    Also, we have starterware example code for timer with internal clock support.

    C:\ti\pdk_C6748_2_0_0_0\C6748_StarterWare_1_20_03_03\build\c674x\cgt_ccs\c6748\lcdkC6748\timer

    Please ask us for any clarification.
  • 0
    Mastermind 6115 points

    Hi Lingling zhan,


    we use the internal clock as the timer clock source,the datasheet said that"The internal clock source to the timer is generated by the PLL controller",But the problem is thart which one of PLL controller outputs is ?how we know what the value of the timer clock?

    Yes, clock source for timer is generated internally through the PLL controller. PLL0 controller output clock (PLL0_AUXCLK) serves as a input for timer.

    That is say What is the logical relationship between CPU clock and timer clock? We hope you help!!

    As timer clock (PLL0_AUXCLK ) is derived directly from OSCIN(oscillator) and it bypass the PLL clock. So Both Timer and CPU will run at same frequency.
    Please check chapter 8(Phase-Locked Loop Controller) of Technical reference manual (spruh77a) for more information.