C6670 CPU frequency increase

Pavlo Sergiienko

Other Parts Discussed in Thread: TMS320C6670

Hi,

I'am using the TMS320C6670 DSP and pdk_C6670_1_1_2_6. And I want to increase the CPU frequency from default 983,04 MHz to 1200MHz as it is allowed in the manual.

So I call the platform_init function like this:

platform_init_flags init_flags;
platform_init_config init_config;
platform_info p_info;

/* Turn on all the platform initialize flags */
memset(&init_config, 0, sizeof(platform_init_config));
memset(&init_flags, 0x01, sizeof(platform_init_flags));

init_flags.phy = 1;
init_config.plld = 1;
init_config.pllm = 20;
init_config.prediv = 1;
init_config.postdiv = 2;
platform_init(&init_flags, &init_config);

In that case the multiplier works just like I wanted. But seems to be that any of the divider is not working at all. Basically I can write whatever I want there and the frequency will be the same. I saw some thread on forum that Keystone I doesn't have Post divider block. Ok. But what with the other two?

The reason I'am asking is that with only a multiplier I can get either 1.2288 GHz (PLLM = 20) or 1.1674 GHz (PLLM = 19). If the first option doesn't count as overclocking then it will do for me, but if it does I wanted to establish PLLM = 39 and PLLD = 2, so the CPU frequency would be like 1.1981 GHz. Clock frequency is 122.88 MHz. Current frequency I'am checking with platform_get_frequency() API.

Best Regards,

Pavlo!

over 10 years ago

0 Senthilkumar Srinivasan over 10 years ago

TI__Mastermind 43660 points

Hello Pavlo,

Yes, in keystone 1 devices, the POSTDIV is not available and valid.

The above mentioned way of passing PLLD value is not allowable in pdk example code as this is set in the library. Please see the below code where you can find PLLM only have an option to get its value either from init_config or from the library.

/* Setup PLLC hardware parameters */        
            pllc_hwSetup.pllM       = 
                    (((p_config->pllm) ? p_config->pllm : PLATFORM_PLL1_PLLM_val) - 1);
            pllc_hwSetup.preDiv   = PLATFORM_PLL_PREDIV_val - 1;
            pllc_hwSetup.pllDiv2  = PLATFORM_PLLDIV2_val - 1;
            pllc_hwSetup.pllDiv5  = PLATFORM_PLLDIV5_val - 1;
            pllc_hwSetup.pllDiv8  = PLATFORM_PLLDIV8_val - 1;
            pllc_hwSetup.postDiv  = PLATFORM_PLL_POSTDIV_val -1;

Also note that, PLATFORM_PLL_PREDIV_val macro is used for PLLD and PLATFORM_PLL_POSTDIV_val is used for OUTPUT DIVIDE. If you want to change the divider value, you can either change it in PLATFORM_PLL_PREDIV_val macro in platform_internal.h library file or change it in the MAINPLLCTL0 register itself.

Regards,

Senthil

0 Pavlo Sergiienko over 10 years ago in reply to Senthilkumar Srinivasan

Intellectual 660 points

Dear Senthil,

Thank you for your answer. I know about that part of the code in the platform_init function and about platform_internal.h defines. But I really don't want to change any of binary libraries. I think I will write my own function platform_init and change the divider there.

But one more question is still renaming: CPU frequency of 1,2288 GHz is already overclocking or not. The reason why I'am asking that in the evmc6670l.gel file there is a table, where 1250 MHz is possible frequency for that CPU with Clock = 100 MHz, PLLM = 24 and PLLD = 0.

Best Regards,

Pavlo!

0 Senthilkumar Srinivasan over 10 years ago in reply to Pavlo Sergiienko

TI__Mastermind 43660 points

Hello Pavlo,

I hope that should be a typo in the GEL file. I will check with the concern team to correct this error.

If your device speed grade supports 1.2GHz, the maximum frequency you are recommended to operate the device is 1.2GHZ only.Please refer section 2.4.3 PLL Settings in device data manual for recommended PLLM and PLLD settings.

When you operate the device at overclocking frequency, the device operation may degrade and it may cause reliability issues.

Hope it helps you.

Regards,
Senthil

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C6670 CPU frequency increase