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Uboot SPI2

Steve Urwin
Prodigy 20 points


Hi,


I am using a Uboot to boot Linux (Debian) on a Beagle Bone Black.


During the boot stage, I want to output some data on SPI2.

However I am unable to read or write to the SPI2 address space (0x481A0110).

I have tried calling my function at different stages of the u-boot process and have no luck.

Iam using the readl and writel functions (in omap3_spi) and direct access.  When I try to access this memory area, the processor hangs and I get the following returned:

READING from 481a0110
data abort
pc : [<9ff6a744>]          lr : [<9ff6a738>]
reloc pc : [<80832744>]    lr : [<80832738>]
sp : 9ef17e50  ip : 0000000f     fp : 00000001
r10: 00000000  r9 : 9ef17ed8     r8 : 4030cdcc
r7 : 9ff9ca6c  r6 : 9ff9c9e4     r5 : 0000000a  r4 : 9ef1aaf8
r3 : 481a0000  r2 : 0000000d     r1 : 00000000  r0 : 00000016
Flags: nZCv  IRQs off  FIQs on  Mode SVC_32
Resetting CPU ...

If I try to access SPI1 (0x48030110), I can happily send data.

Does anybody have any ideas of what I can try?

Regards,

Steve.

  • 0
    TI__Guru 65405 points
    Hi Steve,

    The BeagleBone Black is equipped with AM335x processor which includes two instantiations of McSPI: SPI0 and SPI1. Chip selects 2 and 3 are not pinned out. Are you sure that you are trying to use SPI2?
    Also I suggest you to check the configuration of SPI0 and SPI1. For more details check the AM335x TRM section 24 Multichannel Serial Port Interface (McSPI).

    BR
    Tsvetolin Shulev
  • 0 in reply to Cvetolin Shulev-XID
    Prodigy 20 points
    Hi Tsvetolin,

    Thank you for your reply.

    You are correct, I am trying to use McSPI1 (and not McSPI2 - I copied the UBOOT definition, which gives SPI1 and SPI2 rather than SPI0 and SPI1) at address 0x481a0000 (from memory map in technical reference manual).

    When I use SPI0, as described in section 24, I am able to produce SPI signals. However when I try to change the base address from 0x48030000 to 0x481a0000 the processor hangs with the following output:
    data abort
    pc : [<9ff396ec>] lr : [<9ff6a54c>]
    reloc pc : [<808016ec>] lr : [<8083254c>]
    sp : 9ef17e80 ip : 80000001 fp : 80800020
    r10: 00000001 r9 : 9ef17ed8 r8 : 4030cdcc
    r7 : 9ff9c96c r6 : 9ff9c8e4 r5 : 1f738000 r4 : 9ff9c970
    r3 : 481a0000 r2 : 0000000d r1 : 00000000 r0 : 9ff8e320
    Flags: nZCv IRQs off FIQs on Mode SVC_32
    Resetting CPU ...

    According to Keil, Precise Data Aborts are those generated after performing an instruction side CP15 operation, and all those generated by the MMU:
    alignment faults
    translation faults
    domain faults
    permission faults

    But why would SPI0 work?

    Best Regards,

    Steve Urwin.