Hi,
Can we configure MPAX to create memory region in DDR which can be written by only a specified core?
Creating private cores memories as defined in the chapter 7 of Lab Manual is not sufficient for our use case.
Use case:
[x] Simplified the use case for easier problem description. Its a typical Consumer - Producer problem. Data synchronization is taken care among the cores.
[x] Algorithm 'A' on Core 0 writes to a memory region 'R' for Algorithm 'B' running on Core 1's consumption
[x] Algorithm 'B' running on Core 1 should only read. But we see that Data in Memory region 'R' is corrupted. Let's assume that Algorithm 'B' wrote into the memory region 'R'
[x] Is there anyway we can detect such interference using memory protection unit? Is the permission attributes of MPAXL any use to control which core can access the memory region? The BADDR and RADDR shall point to the same regions, hence are valid.
I am not sure, if this is possible but would be great asset to prevent inter-core interference. Any other ways to detect this interference is also highly appreciated.
CCS: 5.1.1.00031 Sys/Bios: 6_33_06_50 Platform: C6678EVM XDC: 3_23_04_60
Best Regards
Kishor
(Please move to the appropriate forum, if necessary)
