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AM4377 - Reduced Execution Speed for eXecute In Place (XIP)?

James Evans
Mastermind 49692 points
Other Parts Discussed in Thread: AM4377

Hi!

According to the datasheet, the AM4377 supports booting eXecute In Place (XIP) from Serial. I am looking into the boot options for the AM4377, and I want to verify my present understanding.

If a boot device is stated as XIP (i.e.: QSPI, NOR flash) is all execution reduced to the speed of the flash interface for all code that resides in the external flash device? (e.g.: the entire processor execution reduced in speed to the 12MHz x 4 speed of the QSPI?)

Or is it possible for some initial software, stored off the QSPI, to also use the QSPI to copy run-time code from the external device into RAM?

Thanks,

James

  • 0
    TI__Guru*** 125430 points
    First, the QSPI can operate up to 48 MHz (not 12 MHz).

    Along similar lines, you generally have code running from DDR which is clocked at a much slower speed than the processor. Indeed, there is a speed limitation. This is countered by the cache architecture which reduces the number of required accesses to the memory. So the initial cache misses will be slow, but the impact will be greatly reduced by the cache. The overall impact will be very application specific.
  • 0 in reply to Brad Griffis
    Prodigy 90 points
    Our use case: 1) requires low interrupt latency, 2) doesn't need much code space, 3) initial software and run-time software will reside on the same flash device, 3) is size constrained.

    The present plan is to lock time critical parts of the code in cache, and not to use any off-chip DDR. So, to do this, my understanding is we'll need to use initial software to copy the run-time code from flash to RAM. But is this possible if both the inital software and the run-time software reside on an XIP-only interface? (e.g.: QSPI)

    RE: QSPI speed, it looks like the QSPI module can run up to 48MHz (p3673 SPRUHL7C 4/15), but that during XIP use, it runs at 12MHz (p226). Is this right?

    Thanks,
    Brian
  • 0 in reply to Brian Hook
    TI__Guru*** 125430 points

    Brian Hook said:
    The present plan is to lock time critical parts of the code in cache, and not to use any off-chip DDR.

    FYI, you can only lock code in L2 cache, not L1 for Cortex A9.  I suspect this should be sufficient to meet any real-time deadlines.

    Brian Hook said:
    RE: QSPI speed, it looks like the QSPI module can run up to 48MHz (p3673 SPRUHL7C 4/15), but that during XIP use, it runs at 12MHz (p226). Is this right?

    The 12 MHz reference on page 226 is part of the "Initialization" chapter.  This description refers to how the boot ROM is configuring the QSPI.  Usually the boot ROM is configured conservatively for maximum compatibility.  You should be able to crank the QSPI at the full 48 MHz.