After configuring the Emulation Pin Manager and PADCONF muxing for ETM (i.e. pins etk_clk, etk_ctl, etk_d[7:0]), I see a nice 6.5 MHz square wave on a scope at ETK_CLK. This makes sense, since according to the CM_CLKSEL1_EMU register (value 0x03020A50), TRACECLK is derived from SYS_CLK, and I have a 26 MHz square wave at the input to SYS_XTALIN, and SYS_BOOT6 pulled high.
I am trying to increase the ETK_CLK by changing the TRACECLK source from SYS_CLK to EMU_CORE_ALWON_CLK (which is at 400 MHz based on DPLL3 and relevant divider). However, when I update CM_CLKSEL1_EMU to change the TRACECLK source to EMU_CORE_ALWON_CLK, as well as the TRACECLK divider to 4 (i.e. write 0x03022254 to CM_CLKSEL1_EMU), the 6.5 MHz square wave on ETK_CLK goes away and is replaced with a DC signal at 1.8 V. In addition, according to the CM_IDLEST_CKGEN register, EMU_CORE_ALWON_CLK is not active (value of register is 0x0000020B, which means that DPLL3 and DPLL4 are locked, 48 MHz is active, and DPLL4_M2_CLK is active).
How can I use EMU_CORE_ALWON_CLK as the source of TRACECLK?
Thank you.
