Hi all,
I have a weird problem with the EMIF clocking. I have connected parallel DAC to the EMIF interface on the TMS320C6455 DSK Kit from Spectrum Digital. I have configured the EMIF to create DAC clock of 12 MHz using Setup/Hold/Strobe/Turn Around times in asynchronous mode. EMIF clock on the board is supplied externally and ECLKOUT is 96 MHz. When I checked the clock with the oscilloscope, I am getting 12 MHz, however, when I looked a little bit further back in time, there is a pause in a clock. So what happens is that I need a continuous clock of 12 MHz, but instead I am getting 12 MHz, plus random pause of 200 kHz, that repeats itself periodically at about 10.25 kHz I think. I am using DAC to create a modulated signal for the transmitter, so this pause causes "random bits" insertion. The way I write to the EMIF interface is like this:
/* Base address of the EMIFA */
#define EMIFA_CE4_BASE_ADDR (0xC0000000u)
/* Pointer that points to Async start area */
Uint32 *pAsyncData = (Uint32 *)EMIFA_CE4_BASE_ADDR;
// Some other Initialization code
// Read DIP switch (mapped at CE2 address 0xA0000000)
while(1) {
// take next bit in a sequence
pAsynchData[0] = Data;
}
So basically writing to EMIF is done in a while loop. The DIP switches are read once before entering the while loop.
Have anyone ever experienced this problem before? Should I write to EMIF using interrupt or something else instead to avoid clock pauses?
Any help is appreciated. Thanks in advance.
Vladimir
