AM3359 ICE SPI Problem

/*
 *  ======== mutex.c ========
 *  This example shows the use of two tasks and one semaphore to perform
 *  mutual exclusive data access.
 */

#include <xdc/std.h>
#include <xdc/runtime/System.h>

#include <xdc/runtime/Error.h>
#include <ti/sysbios/BIOS.h>
#include <ti/sysbios/knl/Clock.h>
#include <ti/sysbios/knl/Task.h>
#include <ti/sysbios/knl/Semaphore.h>
#include <ti/sysbios/family/arm/a8/intcps/Hwi.h>


#include <xdc/cfg/global.h>

#include "mcspi.h"
#include "evmAM335x.h"
#include "soc_AM335x.h"
#include "interrupt.h"
#include "plat_led.h"
#include "plat_mux.h"


#include "osdrv_mmu.h"
#include "osdrv_mcspi.h"

Void task1(UArg arg0, UArg arg1);
static void McSPISetUp(void);
Void McSPIIsr(UArg a0);


SYS_MMU_ENTRY applMmuEntries[] = {

	{(void*)0x48300000,0},  //PWM - Non bufferable| Non Cacheable
    {(void*)0x48200000,0},  //INTCPS,MPUSS - Non bufferable| Non Cacheable
    {(void*)0x48100000,0},  //I2C2,McSPI1,UART3,UART4,UART5, GPIO2,GPIO3,MMC1 - Non bufferable| Non Cacheable
    {(void*)0x48000000,0},  //UART1,UART2,I2C1,McSPI0,McASP0 CFG,McASP1 CFG,DMTIMER,GPIO1 -Non bufferable| Non Cacheable
    {(void*)0x44E00000,0},  //Clock Module, PRM, GPIO0, UART0, I2C0, - Non bufferable| Non Cacheable
    {(void*)0x4A300000,0},  //PRUSS1 - Non bufferable| Non Cacheable
    {(void*)0x49000000,0},  //EDMA3 - Non bufferable| Non Cacheable
    {(void*)0x4A100000,0},  //CPSW - Non bufferable| Non Cacheable
    {(void*)0xFFFFFFFF,0xFF}
};

/*
MUX_CONFIG iceMux[] = {
    // SPI1 pinmux
    { 0x0994 , 3 , AM335X_PIN_OUTPUT },	//	spi1_d0_mux2/SIMO	mcasp0_fsx
    { 0x0998 , 3 , AM335X_PIN_INPUT_PULLUP },	//	spi1_d1_mux2/SOMI	mcasp0_axr0
    { 0x0990 , 3 , AM335X_PIN_OUTPUT | AM335X_PIN_INPUT_PULLDOWN },	//	spi1_sclk_mux2/CLK	mcasp0_aclkx . IMPORTATN: You need to enable both, input and output. Input clock is feed back into the RX logic of SPI.
	{ 0x099c , 3 , AM335X_PIN_OUTPUT },	//	spi1_cs0_mux4: HVS SPI1 CS in GPIO mode
	{ 0x09A0 , 7 , AM335X_PIN_OUTPUT },	//	gpio3[18]	mcasp0_aclkr -> INDUS_LDn
    { 0xFFFFFFFF , 0 , 0 }
};
*/
//Int resource = 0;
//Semaphore_Handle sem;
Task_Handle tsk1;
unsigned int flagSPI;
unsigned int LED = 0;
unsigned int Data = 0;

//Int finishCount = 0;

/*
 *  ======== main ========
 */
Int main()
{ 
    Task_Params taskParams;

    MMUInit(applMmuEntries);
    //PinMuxConfig(iceMux);
        
    /* Create a Semaphore object to be use as a resource lock */
    //sem = Semaphore_create(1, NULL, NULL);

    /* Create two tasks that share a resource*/
    Task_Params_init(&taskParams);
    taskParams.priority = 1;
    tsk1 = Task_create (task1, &taskParams, NULL);
    

    Hwi_Handle hwi0;
    Hwi_Params hwiParams;
    Error_Block eb;

    Error_init(&eb);
    Hwi_Params_init(&hwiParams);
    hwiParams.arg = 5;
    hwi0 = Hwi_create(125, McSPIIsr, &hwiParams, &eb);
    if (hwi0 == NULL) {
    System_abort("Hwi create failed");
    }


    McSPISetUp();

    BIOS_start();    /* does not return */
    return(0);
}

/*
 *  ======== task1 ========
 */
Void task1(UArg arg0, UArg arg1)
{
	System_printf("enter taskFxn()\n");

	    static Uint8 prevState;

	    while(1)
	    {
	        McSPICSAssert(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

	    	McSPIIntEnable(SOC_SPI_1_REGS, MCSPI_INT_RX_FULL(MCSPI_CHANNEL_1)|MCSPI_INT_TX_UNDERFLOW(MCSPI_CHANNEL_1));

	    	McSPIChannelEnable(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

	    	while(flagSPI);
	    	flagSPI = 1;

	        McSPICSDeAssert(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

	        McSPIChannelDisable(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

	    	if(Data != prevState)
	    	        LEDDIGOUTSetVal((Uint8) Data);
	    	prevState =(Uint8) Data;
	    	LED++;
	    	Task_sleep(1000);

	    }

}

static void McSPISetUp(void)
{
    System_printf("enter McSPISetUp\n");

	McSPI0ModuleClkConfig();

	McSPIPinMuxSetup(MCSPI_INSTANCE_1);

	//McSPICSEnable(SOC_SPI_1_REGS);

	McSPIClkConfig(SOC_SPI_1_REGS, 48000000, 24000000, MCSPI_CHANNEL_1, MCSPI_CLK_MODE_0);

	McSPIWordLengthSet(SOC_SPI_1_REGS, MCSPI_WORD_LENGTH(16), MCSPI_CHANNEL_1);

	McSPIStartBitDisable(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

	McSPIMasterModeEnable( SOC_SPI_1_REGS);

	McSPIMasterModeConfig( SOC_SPI_1_REGS, MCSPI_SINGLE_CH,  MCSPI_TX_RX_MODE, MCSPI_DATA_LINE_COMM_MODE_1, MCSPI_CHANNEL_1);

	McSPITxFIFOConfig( SOC_SPI_1_REGS, MCSPI_TX_FIFO_ENABLE, MCSPI_CHANNEL_1);

	McSPIRxFIFOConfig(SOC_SPI_1_REGS, MCSPI_RX_FIFO_ENABLE,	MCSPI_CHANNEL_1);

}

Void McSPIIsr(UArg a0)
{

    System_printf("enter McSPIIsr\n");

    unsigned int intCode = 0;

        intCode = McSPIIntStatusGet(SOC_SPI_1_REGS);

        while(intCode)
        {
            if(MCSPI_INT_TX_UNDERFLOW(MCSPI_CHANNEL_1) == (intCode & MCSPI_INT_TX_UNDERFLOW(MCSPI_CHANNEL_1)))
            {
            	McSPIIntDisable(SOC_SPI_1_REGS, MCSPI_INT_TX_UNDERFLOW(MCSPI_CHANNEL_1));

            	McSPIIntStatusClear(SOC_SPI_1_REGS, MCSPI_INT_TX_UNDERFLOW(MCSPI_CHANNEL_1));

                McSPITransmitData(SOC_SPI_1_REGS, LED, MCSPI_CHANNEL_1);
            }

            if(MCSPI_INT_RX_FULL(MCSPI_CHANNEL_1) == (intCode & MCSPI_INT_RX_FULL(MCSPI_CHANNEL_1)))
            {
            	McSPIIntDisable(SOC_SPI_1_REGS, MCSPI_INT_RX_FULL(MCSPI_CHANNEL_1));

                McSPIIntStatusClear(SOC_SPI_1_REGS, MCSPI_INT_RX_FULL(MCSPI_CHANNEL_1));

                Data = McSPIReceiveData(SOC_SPI_1_REGS, MCSPI_CHANNEL_1);

                flagSPI = 0;
            }

            intCode = McSPIIntStatusGet(SOC_SPI_1_REGS);
        }
}