EDMA 3

I am find EDMA3 Channel Synchronization Events table for TMS320C6424 DSP in SPRUEM5A, but i can not find this information in sprufl1c for C6745 DSP. Where i can find this information?
Thanks.

Ok, thanks.

I don't understand the next:

CSL_FINST(edma3ccRegs->DMAQNUM[1], EDMA3CC_DMAQNUM_E2, Q0);  // Assign Channel 10 to Queue 0

Why  all  EDMA3CC_DMAQNUM  values  are zero ?

Is it correct ?

Thanks.

Ok, Thank You, Randy.

I am find the next example  "c6747_audio_edma_v4.zip"  -

I want modify this example for my DSK, but there is a "lack of understanding" about how it works.

#define EDMA_XMTPING         32

#define EDMA_XMTPONG         33

#define EDMA_RCVPING         34

#define EDMA_RCVPONG         35

// 1. setup channel PaRAM slot

   param.OPT = (EDMA_XMT_PING_TCC << 12) | (1 << 20);      // transfer complete interrupt enabled

   param.SRC = (Uint32)src_ping_L;

   param.A_B_CNT = (2 << 16) | sample_size;                // actual format: BCNT|ACNT

   param.DST = (Uint32)dst;

   param.SRC_DST_BIDX = (0 << 16) | ping_offset;           // actual format: DSTBIDX|SCRBIDX

   param.LINK_BCNTRLD = (2 << 16) | (EDMA_XMTPONG * 0x20); // actual format: BCNTRLD|LINK

   param.SRC_DST_CIDX = (0 << 16) | (ping_c_idx & 0x0000FFFF); // actual format: DSTCIDX|SRCCIDX

   param.CCNT = sample_count;

   edmaWritePaRAM(EDMA_MCASPTXCH, &param);

1) Why    EDMA_XMTPING   ->  32,  EDMA_XMTPONG  ->  33    etc.  What means these numbers?

2)  param.LINK_BCNTRLD = (2 << 16) | (EDMA_XMTPONG * 0x20); // actual format: BCNTRLD|LINK

(EDMA_XMTPONG * 0x20) is a Link Address. 

0x20 in this entry means 32-byte PaRAM set.  My understanding is correct ? 

I am reading the next:

16.2.3.2.12 Link Address (LINK)
The EDMA3CC provides a mechanism, called linking, to reload the current PaRAM set upon its natural
termination (that is, after the count fields are decremented to 0) with a new PaRAM set. The 16-bit
parameter LINK specifies the byte address offset in the PaRAM from which the EDMA3CC loads/reloads
the next PaRAM set during linking.
You must program the link address to point to a valid aligned 32-byte PaRAM set. The 5 LSBs of the LINK
field should be cleared to 0.
The EDMA3CC ignores the upper 2 bits of the LINK entry, allowing the programmer the flexibility of
programming the link address as either an absolute/literal byte address or use the PaRAM-base-relative
offset address. Therefore, if you make use of the literal address with a range from 4000h to 7FFFh, it will
be treated as a PaRAM-base-relative value of 0000h to 3FFFh.
You should make sure to program the LINK field correctly, so that link update is requested from a PaRAM
address that falls in the range of the available PaRAM addresses on the device.

A LINK value of FFFFh is referred to as a NULL link that should cause the EDMA3CC to perform an
internal write of 0 to all entries of the current PaRAM set, except for the LINK field that is set to FFFFh.
Also, see Section 16.2.5 for details on terminating a transfer.

But I don't understand how works this entry:   EDMA_XMTPONG * 0x20. I do not have a full understanding how linking mechanism works.

Your help will save me a lot of time.

Thanks.

I find a good explanation for resolving my problem.

This is article  "StarterWare Audio Application"   .

 In c6747_audio_edma  example we have a similar idea.

 The paRAM set EDMA_RCVPONG is linked to paRAM set EDMA_RCVPING, which is initialized to receive data in rcv_pong. The paRAM set EDMA_RCVPING is linked back to paRAM set EDMA_RCVPONG. Hence the reception paRAM set is initialized as: 

EDMA_RCVPONG --> EDMA_RCVPING --> EDMA_RCVPONG. 

My understanding is correct ?

2) 

#define EDMA_XMTPING 32
#define EDMA_XMTPONG 33
#define EDMA_RCVPING 34
#define EDMA_RCVPONG 35

Numbers in this defines can be any  from 0 to 127. Is it correct ?

Hi.

I can't  find  Channel Options Parameter (OPT) register in CCS v5.5 for EDMA 3.

How to check its parameters on Debug mode ?

Thanks.

Hi Arvind,

Thanks for your detailed explanation. It's really works, but i have some problem.

In OPT register I have always value  0x40019B00. (After  reset, after config param OPT etc).

For example:

CSL_FMKT(EDMA3CC_OPT_TCINTEN, ENABLE)  ->  set  TCINTEN bit in OPT register.

But I have the next: 

0x40019B00_hex  ->   1000000000000011001101100000000_bin  (TCINTEN bit = 0)

May be I'm doing something wrong?

Thanks.

0x01C00000  is not OPT address.

I am find the next:

Parameter set 10 -> Byte address 0x01C04200

In Memory  Browser  i have the next:

It does not correspond to the required values.

I checked the values of Timer64_P0 registers in memory browser  - it is ok.

May be I am wrong .