AM437x and Micron DDR3L routing and layout

Eshak B

Hi,

In our design we are using two DDR3L chips each of 2Gb placed back to back on PCB.

We are considering the AM437x datasheet and general guidelines for DDR3 routing.

Due to space constraint and datalines crossing over, we have planned to swap the data lines within byte except for D0 and D8 connected as it is to processor controller for 1st DDR3L. Similar connection done for 2nd DDR3L also.

1. Please confirm whether data swapping is fine with in each byte?

2. Whether software wise any thing need to be taken care for this change?

Regards

B. Eshak

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Eshak,

Are D8 and D15 connected 1:1 too on the second DDR?

0 Biser Gatchev-XID over 10 years ago in reply to Biser Gatchev-XID

TI__Guru**** 393215 points

Sorry, I didn't see that you have mentioned D8 in your post. My question about D15 is irrelevant. Yes, this should be OK, since bits are only swapped within the byte lane they belong to.

0 Eshak B over 10 years ago in reply to Biser Gatchev-XID

Intellectual 585 points

Hi Biser

Thanks for the reply.
Just to be confirmed, i m mentioning you the actual connection between Processor SDRAM and DDR3L devices.

For DDR3l-1
----------------
(Processor) (DDR3L device)
DDR_D0----> DQL0 (fixed)
DDR_D1----> DQL3
DDR_D2----> DQL1
DDR_D3----> DQL6
DDR_D4----> DQL7
DDR_D5----> DQL5
DDR_D6----> DQL4
DDR_D7----> DQL2

DDR_D8----> DQU0 (fixed)
DDR_D9----> DQU1
DDR_D10----> DQU2
DDR_D11----> DQU6
DDR_D12----> DQU4
DDR_D13----> DQU5
DDR_D14----> DQU3
DDR_D15----> DQU7

Is there any software need to configure on the processor side for this change.
Please confirm.

Regards
B. Eshak

0 Biser Gatchev-XID over 10 years ago in reply to Eshak B

TI__Guru**** 393215 points

Yes, this should work. I suppose DQS0/DQS0n and DM0 are routed along with D[7:0] and DQS1/DQS1n and DM1 are routed along with DQ[15:8]? If that is so there will be no problems.

0 Eshak B over 10 years ago in reply to Biser Gatchev-XID

Intellectual 585 points

Yes, DQS0/DQS0n and DM0 are routed along with D[7:0] and DQS1/DQS1n and DM1 are routed along with DQ[15:8]

Thank you for the support

Regards
B. Eshak

0 Eshak B over 10 years ago in reply to Biser Gatchev-XID

Intellectual 585 points

Dear Biser

With respect to earlier discussion on this within byte swapping, I have one clarification with respect to software configuration.

Since now the bit within byte has been changed due to layout routing, how the software team need to configure so that the data read and write is proper.

Please explain briefly.

Thank you

Regards

B. Eshak

0 Biser Gatchev-XID over 10 years ago in reply to Eshak B

TI__Guru**** 393215 points

No software intervention is necessary. From the processor point of view if you write on bit 6 and it goes to bit 3 of the DDR, then when you read from the same DDR address the contents of bit3 from the DDR will be read into bit 6 of the processor.

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AM437x and Micron DDR3L routing and layout