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DM 8168 DDR init issue

Pradipsinh Parmar
Prodigy 70 points

I am trying to connect spectrum degital xds200 emulatore as jatag with DM8168 Processore,

I am having below error, any one please help on this, my board is not booting up.

CortexA8: Trouble Writing Memory Block at 0x4c000010 on Page 0 of Length 0x4: (Error -2130 @ 0x4C000010) Unable to access device memory. Verify that the memory address is in valid memory. If error persists, confirm configuration, power-cycle board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
CortexA8: GEL: Error while executing OnTargetConnect(): Target failed to write 0x4C000010 at *((unsigned int *) (0x4C000000+0x10))=(unsigned int) (0x10000000|SDREF) [evm816x.gel:325] at EMIF4P_Init(0x1779C9FE, 0x50608074, 0x009F857F, (0x10001841&0xfffffff), 0x62A73832, 0x00000310) [evm816x.gel:1328] at Setup_DDR() [evm816x.gel:47] at OnTargetConnect() .
CortexA8: Trouble Reading Register CP15_Registers_CP15_CONTROL_REGISTER: (Error -2131 @ 0x20013F00) Unable to access device register. Reset the device, and retry the operation. If error persists, confirm configuration, power-cycle the board, and/or try more reliable JTAG settings (e.g. lower TCLK). (Emulation package 5.1.232.0)
CortexA8: Error: (Error -1045 @ 0xFFFFFF4C) The emulator reported an error. Confirm emulator configuration and connections, reset the emulator, and retry the operation. (Emulation package 5.1.232.0)
CortexA8: Failed to remove the debug state from the target before disconnecting. There may still be breakpoint op-codes embedded in program memory. It is recommended that you reset the emulator before you connect and reload your program before you continue debugging.

 

 

  • 0
    TI__Guru**** 170625 points
    Hi Pradipsinh,

    Are you using DM816x TI EVM or custom board? Make sure you are following the below procedure, it is for Blackhawk USB 560M JTAG emulator, but should be similar for SD XDS200.

    e2e.ti.com/.../1517723

    See also if the below wiki pages will be in help:
    processors.wiki.ti.com/.../Files_in_CCS_Projects
    processors.wiki.ti.com/.../XDS100

    BR
    Pavel
  • 0 in reply to Pavel Botev
    Prodigy 70 points
    Hi Pavel,

    I am using custom board, and the process I am following is also same as you suggest, I am trying to boot the board from SD card, and there is some issue in DDR3, so it can not communicating properly with processor,
    What should be the problem if DDR3 is not coming out off RESET, I have doubt on RESET# pin of DDR.
    Please suggest me further if you have any issue related this.

    Regards,
    Pradipsinh
  • 0 in reply to Pradipsinh Parmar
    TI__Guru**** 170625 points

    Pradipsinh,

    Pradipsinh Parmar said:
    I am trying to boot the board from SD card

    Can you provide me the boot log?

    Regarding DDR3 issues, I would recommend you to try with the HW diagnostic test from Spectrum Digital:

    Test Code -> tests -> ddr (Test DDR memory, checks the data and address lines are good)

    See also DM816x TI EVM reference schematics and DM816x datasheet, 9.3.2 DDR3 Routing Specifications


    BR
    Pavel

  • 0 in reply to Pavel Botev
    Prodigy 70 points

    Hi Pavel,

    Board boot up with internal memory but not booting with DDR3.

    We have done Software leveling in this but still its not working.

    In Past we were made same board and that all are working fine,

    at this time we have change version of SOC,

    can you tell me that what is different between TMS320DM8168BCYG2 and TMS320DM8168SCYG2 ??

    Can you please provide me errata for the same ?

  • 0 in reply to Pradipsinh Parmar
    TI__Guru**** 170625 points

    Hi Pamar,

    The difference between BCYG2 and SCYG2 is that first one is 2.0 silicon revision, second one is 2.1 silicon revision.

    What is the u-boot version you are using? Try with the latest u-boot code base:
    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=shortlog;h=refs/heads/ti81xx-master

    Make sure at least you have the below patch in your u-boot code base:
    http://arago-project.org/git/projects/u-boot-omap3.git?p=projects/u-boot-omap3.git;a=commit;h=ca8a79a7462192d92106673fe4d62d48aee05624

    The difference between 2.0 and 2.1 devices are described in the DM816x silicon errata:
    www.ti.com/.../sprz329f.pdf

    In section 2.2 are described silicon errata bugs for all silicon revisions (2.1, 2.0) and in section 3 are described silicon errata bugs which are fixed for 2.1 rev

  • 0 in reply to Pavel Botev
    Prodigy 70 points

    Hi, 

    This issue is resolve,

    There is problem in DDR timing,

    We have done SW leveling.

    Thanks for support

    Regards,

    Pradipsinh Parmar