C66x PCIe Root Complex internal architecture

Clement FR

Hello everyone,

Target is C6678.

I have a question about the PCIe architecture for this device.
I didn't find answers about it in the User Guide, nor the wiki nor the forum

To me the C66x Root Complex architecture (inside "PCIe core") is like this

It's the user responsability (or operating system enumeration software) to generate
a Type 0 configuration request targeting BDF 0/0/0 to setup the Primary/secondary/subordinate bus values and other things.

Tell me if I'm wrong.

Also sometimes in the PCIe classic litterature (for example PCI Express Technology book) the Root Complex is shown like this

Can you confirm to me that in the C66x root complex architecture
there is no secondary and subordinate bus to set up in the Host/PCIe bridge ?

Thank you
Regards,

Clement

over 10 years ago

0 Ganapathi Dhandapani95 over 10 years ago

TI__Mastermind 28085 points

Hi,

The bus enumeration is usually done by the system's firmware/device drivers or the operating system in the host/Root Complex. TI doesn’t provide PCIE RC enumeration driver.

Have you referred the below e2e thread?
e2e.ti.com/.../901027

Thanks,

0 Clement FR over 10 years ago in reply to Ganapathi Dhandapani95

Genius 4750 points

Hello Ganapathi,

Thank you for the link.

Here's the discussion is only about the internal PCIe architecture of the PCIESS for C66x devices.

It's for a better understanding of the architecture. I'm not talking about enumeration here.

Clement

Processors

Processors forum

C66x PCIe Root Complex internal architecture