Hi,
I have question about AM335x non-muxed XIP Boot.
In TRM(spruh73l) page.4926 "26.1.7.2.2 Pin used", it said as follows;
//////////////////////////////////////////////////////////////
Specifically, external logic is needed to isolate the upper address lines (A12-A27) of the NOR flash
from the device pins and drive them low during non-muxed NOR boot.
//////////////////////////////////////////////////////////////
So, I guess bus-switch can be the solution for isolate the upper address and drive those address lines low.
The connection between GPMC and NOR Flash will be like follows:
A0 to A11 : directly connected
A12 to A27 : connected via bus switch
But the pattern length will be diffent because of bus-switch.
My customer is concerned whether the gap of the timing occurs for this patterh length difference or not.
After XIP boot, would this become a problem for GPMC operation against NOR Flash?
Or can this gap of timing be ignored and it will not influence to GPMC operation?
best regards,
g.f.
