Hi,
My project contains two TI DSP C6674 processors, which are enabled with Ethernet and SRIO communication. Ethernet and SRIO both are working.
Each DSP has DDR3 of size 2GB, where 1GB is used for SRIO communication. During SRIO interface bringup, I came to know that to work with SRIO, SRIO memory region should be cache disabled, so for that reason i disabled cache for SRIO memory.
Ethernet throughput got effected with this change i.e., :
Disabled cache of 2GB DDR3, Ethernet throughput : 80Mbps
Disabled cache of 1GB DDR3, Ethernet throughput : 150Mbps
Enabled cache of DDR3, Ethernet throughput : 300Mbps
My Hardware Ethernet supports a data speed of 1Gbps
I would like to know is this the same expected as per DSP Processor design or do I need to modify my application?
and also, Does TI/anyone has any practical Ethernet throughput observation for above cases?
Awaiting for your response
Thanks