Keystone II DDR3 Memory Controller documentation issue - SPRUHN7C

Topi Rinkinen

Hi,

SPRUHN7C, on table 4-2 (page 47), says:

1C4 - DX0GSR0

1C8 - DX0GSR1

OTH, 4.63 (page 122) and 4.64 (page 123) describes DXnGSR0 and DXnGSR2. The text here says there are 3 registers DXnGSR0-2, but only 2 of them (0&2) are documented, and different set of 2 (0&1) are listed in address table (4-2).

Easy assumption is that 4.64 is describing DXnGSR1, and DXnGSR2 does not exist. What is the reality?

BR, -Topi

over 10 years ago

0 Aditya over 10 years ago

TI__Expert 6815 points

Hi,
4.63 & 4.64 describe DXnGSR0 & DXnGSR2 respectively. The text should say DXnGSR0 & 2, not DXnGSR0-2. We will remove references to DXnGSR1 from the next revision. Sorry for the confusion!

0 Topi Rinkinen over 10 years ago in reply to Aditya

Prodigy 220 points

I assume this means that offset 0x1C8 should reference to DX0GSR2, not DX0GSR1 (as stated on page 47). Right?

BR, -Topi

0 Senthilkumar Srinivasan over 10 years ago in reply to Topi Rinkinen

TI__Mastermind 43660 points

Hello Topi,

Yes, the offset 0x1C8 referencing to DX0GSR2 and not DX0GSR1. As Aditya mentioned in above post, it will be corrected in next version.

Regards,
Senthil

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Keystone II DDR3 Memory Controller documentation issue - SPRUHN7C