custom board based on AM3352 with MT41K128M16JT-125M:K DDR3

pavan krishna

Dear All,

We have beagle bone black prototyped custom board, where we replaced the existing DDR with "MT41K128M16JT-125M:K DDR3". We are usingDDR3L-1600 Speed Bins. We are trying to update the timing parameters in DDR3 timing configuration tool spread sheet, in the process we have ambiguities on below timing parameters; Please clarify us.

tRRD
ODTLon
tXP

I have attached MT41K128M16JT-125M:K DDR3 datasheet and also updated spread sheet please verify and correct me.

Please provide me the values which I should choose for the below parameters.

CL? (For BBB they chosen CL=6, what should I choose for my DDR3L-1600 Speed Bins and how to choose )
AL?

Thanks in advance,

AM335x_DDR_register_calc_tool_tunstall.xls 2Gb_1_35V_DDR3L.pdf

over 10 years ago

0 Biser Gatchev-XID over 10 years ago

TI__Guru**** 393215 points

Hi Pavan,

Your DDR is identical with the one used in BBB, except for size. You have correctly chosen tRFC and tXS values for your size. Only error I see is tRRD, which should be 4. All other values you can keep the same as in BBB.

0 pavan krishna over 10 years ago in reply to Biser Gatchev-XID

Expert 1010 points

Thanks a lot Biser for your reply and confirmation,

I will correct tRRD. Can u you please explain, how to choose CL value and AL value? In BBB it's value is 6, even I kept the same value, please explain me how to choose this value?

0 Biser Gatchev-XID over 10 years ago in reply to pavan krishna

TI__Guru**** 393215 points

Check Table 54 in the DDR datasheet. You will see that CL=6 is for tCK from 2.5ns to 3.3ns, which is the AM335X use case (DDR3 clock from 303MHz to 400MHz).

0 pavan krishna over 10 years ago in reply to Biser Gatchev-XID

Expert 1010 points

Fine, Thanks a lot
I am on the same page. Can you please provide some good links to verify my newly configured DDR3 is working fine or not?

AL also please?

I checked the below link
processors.wiki.ti.com/.../Sitara_Linux_Training:_Tuning_the_DDR3_Timings_on_BeagleBoneBlack.
Share me if you have any other links.

0 Biser Gatchev-XID over 10 years ago in reply to pavan krishna

TI__Guru**** 393215 points

This is the correct link.

0 pavan krishna over 10 years ago in reply to Biser Gatchev-XID

Expert 1010 points

Biser,

Can you please explain how to determine "MT41K128M16JT125M_EMIF_READ_LATENCY" register value?

0 Biser Gatchev-XID over 10 years ago in reply to pavan krishna

TI__Guru**** 393215 points

Just leave it as it is.

0 pavan krishna over 10 years ago in reply to Biser Gatchev-XID

Expert 1010 points

Thank you,
Sure, Can you please kindly explain me?
I have followed the below link, there is no complete info available.
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM335x_DDR_PHY_register_configuration_for_DDR3_using_Software_Leveling

My confusion is in GEL file I have updated Read latency as 0x07

=====================================================================

#define ALLOPP_DDR3_READ_LATENCY 0x07 //RD_Latency = (CL + 2) - 1

=====================================================================

but in my u-boot source code should i update MT41K128M16JT125M_EMIF_READ_LATENCY as 0x07 or 0x100007.

if it is 0x100007, why?

=====================================================================

#define MT41K128M16JT125M_EMIF_READ_LATENCY 0x100007

=====================================================================

Thank U,

0 Biser Gatchev-XID over 10 years ago in reply to pavan krishna

TI__Guru**** 393215 points

Correct value is 0x100007. Just follow the steps described in the tutorial.

0 Geoffrey Lansberry over 9 years ago in reply to Biser Gatchev-XID

Intellectual 905 points

Biser - I've been poring through the tutorial as you suggested to the previous question-asker, trying to find where it describes how to come up with the 0x100007 instead of 0x07 for ALLOPP_DDR3_READ_LATENCY. The best I can find are the instructions in the gel file which clearly say to do that simple math, which would never result in the larger number. I don't want to just OR in 0x100000, I want to understand why. I see in the ddr_defs.h file that the larger number is not always the case. Can you help clarify or provide a link that does?

Thanks

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custom board based on AM3352 with MT41K128M16JT-125M:K DDR3