DM8148 - Optimising tCH(avg) and tCL(avg)

Padmanabhan KS

Hello All

We are working on custom board using DM8148 with DDR3 chips. We make use of the DDR0 interface only.

On our prototype, on measuring the DDR Clock signal using a differential probe, we notice that there is (a) very little margin on tCH(avg) and tCL(avg) values using DDR chip for one manufacturer. (b) fail tCH(avg) and tCL(avg) measurements on measuring using our second source chip.

I have atatched the screenshots of the measurement data from the report.

Marginal Pass:

Failed Measurement:

Other measurements using the Test Suite from LeCroy's DDR3 measurement software look ok with sufficient margin. Both the boards are working fine and we do not have functionality issues with respect to DDR.

We used the DM814x_DDR_Controller_Register_Configuration_spreadsheet_v1.0 from TI to generate the register values. The input to the excel sheet were based on the DDR device datasheet.

Can somebody tell me which register values might need to be tweaked so as to get the correct clock signal symmetry. Does this relate to the slew rate of Clock signal?

Thanks.

Regards,

Padmanabhan

over 9 years ago

0 Pavel Botev over 9 years ago

TI__Guru**** 170625 points

Hi Padmanabhan,

You can check DM814x TRM, section 7.6.2. Check also SDRAM timing registers (SDRTIM1/2/3).

See also if the below wiki pages will be in help:
processors.wiki.ti.com/.../AM335x_EMIF_Configuration_tips
processors.wiki.ti.com/.../AM437x_DDR_Configuration_and_Programming_Guide

BR
Pavel

0 Padmanabhan KS over 9 years ago in reply to Pavel Botev

Intellectual 510 points

Hi Pavel

Thanks for the reply.

We shall review the register settings.

Apart from that, does the DM8148 have any spec on the output duty cycle for the DDR Clock with maximum tolerances?

Regards,

Padmanabhan

0 Pavel Botev over 9 years ago in reply to Padmanabhan KS

TI__Guru**** 170625 points

Padmanabhan,

Please refer to the below e2e thread:

e2e.ti.com/.../974740

BR
Pavel

0 Padmanabhan KS over 9 years ago in reply to Pavel Botev

Intellectual 510 points

Hi Pavel

Does this mean the upper and lower limits for t(Ch)avg and tCL(avg) is 0.53* tCK and 0.47*tCK respectively?

We have been doing some measurements on the DDR clock and find that the average high and average low pulse width are slightly outside these limits although board is functional.

Is there any register to specifically control the clock parameters such as duty cycle or pulse width? I can't find any in the TRM/DM. Or is there any way to eliminate any measurement issue?
Regards,
KS.Padmanabhan

0 Padmanabhan KS over 9 years ago in reply to Padmanabhan KS

Intellectual 510 points

Hi Pavel

I did some more measurements on another PCBA.

To isolate the problem, the Clk line was cut between the memory controller and DDR chips and terminated with 50 ohms to GND for testing purposes. The setup is like shown below.

With the above setup also, the high and low pulse widths of DDR clock are uneven. The measurement show that the high pulse width is slightly above marginal pass condition of tCH(avg) which is 0.47*tCK. Below is the waveform

Measurement were carried out with a 4GHz active differential probe with Solder-in Tip.

This seem to point out that the output clock from DM8148 itself is uneven. Is there anything that can be done to even this out?

Regards,

K.S.Padmanabhan

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DM8148 - Optimising tCH(avg) and tCL(avg)