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TMDX320CI6614 EVM - RF Board integration

Amit Shenoy
Prodigy 100 points
Other Parts Discussed in Thread: TMS320TCI6614

1) Is there any clock that need to be provided to EVM when EVM – RF Board is connected via optical cable

2) Are there any registers in PHY and AIF2 registers that can be monitored to check the AIF2 link status ie to know if sync is achieved or not. In case there are errors observed in AIF2 registers or PHY, then what does it correspond to and how can the info be used to understand why the sync is not happening or resolve the sync

3) Assume in EVM-RF Board combination, EVM is always CPRI master and is the default config – can this be confirmed

4) How to set the default CPRI link rate to 2.46 Gbps?

  • 0
    TI__Mastermind 43660 points
    Hello Amit,

    Welcome to the TI E2E forum. I hope you will find many good answers here and in the TI.com documents and in the TI Wiki Pages (for processor issues). Be sure to search those for helpful information and to browse for the questions others may have asked on similar topics (e2e.ti.com).

    We are working on this post and get back to you soon.

    Regards,
    Senthil
  • 0 in reply to Senthilkumar Srinivasan
    Prodigy 100 points

    Hi Senthil,

    Can it be verified whether CPRI rate 3 i.e. 2.46 Gbps can be supported at all. This is of the most importance to us currently. Would appreciate your feedback.

    Regards,

    Amit

  • 0
    TI__Mastermind 21025 points
    Hi Amit, I will try to answer your questions. First, let me point you to several resources available for AIF2. AIF2 is a very complex peripheral, so your team should plan to spend quality time with these!

    1) AIF2 User Guide. Contains programming information, CPRI and timing information, examples, and much more. Search for SPRUGV7 at ti.com.
    2) TMS320TCI6614 Datasheet. Contains AIF2 and device level information. Search for SPRS671D at ti.com.
    3) AIF2 LLD and CSL. The is the AIF2 driver that is built on top of the CSL – register and field access routines. Also included are example programs that will help you get up and running. This should come with your device, and can be downloaded from ti.com.

    Question 1: A clock required?

    The interface between AIF2 and the outside world is the AIF2 SerDes, consisting of two macros (B4 and B8) that control the operation of the 6 AIF2 lanes/links. For CPRI you normally need a 245.76Mhz system clock, provided by the LVDS to the AIF2 SerDes (see AIF_REFCLK in Figure 7-2 of the user guide). However, for the 2.46Gbps rate you want, you’ll need to provide a 307.2MHz clock (CPRI 5x). See user guide sections 7.3, 7.4 and 8.x, and datasheet section 8.3 for more details.

    Question 2: Registers to provide link status?

    Yes, the RM and EE modules contain link status registers that can be used to monitor the health of the link. I would recommend reading the related sections of the user guide. The rest of this question is too broad to answer, your answers are most likely in the user guide.

    Please understand that most AIF2 registers simply initialize as zero, and this does not constitute a valid configuration. In fact, the AIF2 peripheral defaults to powered off at chip reset. You must power up and then configure the AIF2 following a reset, unless perhaps you are relying on another software layer to initialize AIF2 for you. We strongly recommend using the AIF2 LLD for initialization and configuration.

    Question 3: EVM is CPRI Master?

    AIF2 can be configured as either master or slave, there is no hardware default. See section 5.2.4 of the user guide, it provides sequences for CPRI Timing as either master or slave.

    Question 4: How to set default CPRI link rate of 2.46Gbps?

    As mentioned above, you’ll need to provide a system clock of 307.2MHz to the AIF2 SerDes. Then program the various AIF2 modules for CPRI 5x. You will find link rate registers in these modules: SD, RM, TM, CI, CO, RT, PD, PE. You will find it much easier to take an existing example and modify it per your requirements.
  • 0 in reply to db_woodall
    Prodigy 100 points
    Thanks for the clarifications! However, we have one specific question-
    We have a binary version (LWP1410) of LTE PHY made available by TI, which I believe, will have the configurations and drivers you mentioned built into it already. It is in this scenario that we wanted clarification on the CPRI link rates supported and one configured to be used.

    Thanks!

    Regards,
    Amit
  • 0 in reply to Amit Shenoy
    TI__Mastermind 21025 points

    I looked through the docs in LWP1410, and the AIF2 configuration is for CPRI line rate of 2.46Gbps, so you should be okay.

  • 0 in reply to db_woodall
    Prodigy 100 points

    Thank You very much!

    Wrt info from PHY, can u tell us the variables to be looked into to check AIF2 sync status ie to know if PHY detects if sync is achieved or not. In case there are errors observed in AIF2 registers or PHY, then what does it correspond to and how can the info be used to understand why the sync is not happening or resolve the sync

    Regards,

    Amit

  • 0 in reply to Amit Shenoy
    TI__Mastermind 21025 points

    First, you should understand what type of error reporting is provided by the library you are using. Second, have a look at Tables 8-30 through 8-34 of the AIF2 user guide. These are the 5 RM Link Status registers available for each of the 6 links (though probably only link 0 is active).  As I mentioned before, it is not possible to discuss these register interactions in the forum - this is the purpose of the user guide.

    I will say though, that AIF2 can recover from many situations where loss of signal (LOS) or loss of frame (LOF) is detected. So you may temporarily (for a frame or two) see packets stop flowing, then will restart and you check the link status (say field 'sync_status' in RM Link Status Reg 0) and see that it shows "ST3" (normal operation state).

  • 0 in reply to db_woodall
    Prodigy 100 points
    One more clarification, going back to my post of June 16, 2015 on clock requirement.

    e2e.ti.com/.../760907
    This post says that the SCBP board requires a external 10 MHz reference clock plugged onto a connector on the board, presumably directly from the EVM master source. Is this a limitation with the CPRI implementation on SCBP? I understand that typically, the clock has to be recovered from the bit transitions of the CPRI link. Would appreciate some more information on this.

    Thanks!

    Regards,
    Amit
  • 0 in reply to Amit Shenoy
    TI__Mastermind 21025 points

    I don't understand the question.  The 10Mhz clock is particular for that hardware configuration.