Hi Experts,
Im using AM4377 processor, in order to calculate the DDR3 timing window, i require the total setup/hold consumed by Transmitter (AM4377). But in the ARM4377 datasheet i could see "For the LPDDR2, DDR3, and DDR3L memory interfaces, it is not necessary to use the IBIS models to analyze timing characteristics. TI provides a PCB routing rules solution that describes the routing rules to ensure the memory interface timings are met" , which means i don't need to find the timing margin for Transmitter + Interconnect + Receiver (SDRAM). Could someone clarify.
