c6748 EDMA

James Alford

Other Parts Discussed in Thread: PCM3168A, SRC4392, OMAP-L138, OMAP-L137, TMS320C6747, OMAPL138

Hi,

I had some questions about c6748 EDMA3. I have been modifying a working code example for a TMDXLCDK6748 from Donald Reay's book "Digital Signal Processing and Applications with the OMAP-L138 eXperimenter". I have had this example running successfully on the TMDXLCDK6748 and implemented some FIR filters etc which work well. I have also designed and built an expansion board for the TMDXLCDK6748 with a PCM3168A CODEC and SRC4392 and I want to modify the code example to support the extra inputs/outputs. I am trying to modify the EDMA programming to do this.

After modifying the EDMA PaRam sets, they are not generating the required interrupt on transfer completion as they previously did. I know this application is a support nightmare so I am trying to figure it out.

I've been referring to the document "SPRUFL1C" which is also more usefully titled:

"TMS320C6747/45/43 and OMAP-L137 Processor Enhanced Direct Memory Access (EDMA3) Controller User's Guide"

and also the EDMA video series here:

https://training.ti.com/using-c6000-edma3-part-2-14-15

Is "SPRUFL1C" applicable to the c6748? I can't find anything closer. Any tips on other resources or things to check?

I thought it shouldn't be too difficult if I just program the PaRAM set to generate the same interrupt as it was previously-right?

Regards,

James

over 10 years ago

0 Titusrathinaraj Stalin over 10 years ago

TI__Guru** 116100 points

Hi,
We have separate EDMA user guide document for OMAPL138/C6748 devices.
Here you go.
www.ti.com/lit/ug/sprugp9b/sprugp9b.pdf

Also, please refer to the following useful TI wikis for EDMA.

processors.wiki.ti.com/.../EDMA3
processors.wiki.ti.com/.../Programming_EDMA_without_EDMA3LLD_package
processors.wiki.ti.com/.../Programming_the_EDMA3_using_the_Low-Level_Driver_%28LLD%29

I have also designed and built an expansion board for the TMDXLCDK6748 with a PCM3168A CODEC and SRC4392 and I want to modify the code example to support the extra inputs/outputs.

Have you routed the audio pins correctly and able to see the expected signals ?

After modifying the EDMA PaRam sets, they are not generating the required interrupt on transfer completion as they previously did. I know this application is a support nightmare so I am trying to figure it out.

You are facing issues just with not generating "completion interrupt" alone and transfer get completed successfully ?
Which examples are you using ?

Could you show the recent changes you made also with previous one.

0 James Alford over 10 years ago in reply to Titusrathinaraj Stalin

Prodigy 50 points

Update: I have realized there are other problems to fix before the EDMA issues. I have determined the AIC3106 codec on the TMDXLCDK6748 is operating as the MCASP master- despite what the comments in the code example from the text say. Here is the configuration code for the MCASP, EDMA, PCM3168A, SRC4392 and AIC3106. This code works ok as is with just the AIC3106 codec working..

// L138_LCDK_aic3106_init.c
//
// triple buffer edma version

#include "L138_LCDK_aic3106_init_triple.h"

int16_t *tempptr, *inptr, *outptr, *procptr;

int16_t *aic3106_input_A, *aic3106_input_B;
int16_t *aic3106_output_A, *aic3106_output_B;

int16_t *analog_input_A, *analog_input_B;

int16_t *digital_input_A, *digital_input_B;

int16_t *analog_output_1_2_A, *analog_output_1_2_B, *analog_output_3_4_A, *analog_output_3_4_B;
int16_t *analog_output_5_6_A, *analog_output_5_6_B, *analog_output_7_8_A, *analog_output_7_8_B;

int16_t *digital_output_A, *digital_output_B;

extern void vectors(void);


void EDMA3_PaRAM_setup() // sets up PaRAM and enables EDMA events
{
uint32_t *EDMA3_PaRAM_ptr;
// PaRAM sets (channels) 0 and 1, triggered by McASP0
// receive and transmit events respectively, are used
// with linked parameters set up in PaRAM sets (channels) 64, 65, 67, and 68
// the linked parameters differ only in the ping or pong buffers used

// set up PaRAM set 1 (MCASP0 XEVT)

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04020);

*EDMA3_PaRAM_ptr++ = 0x00000000; // no EDMA3 interrupts on transfer complete
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr; // source is one of two output buffers
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
// BCNT = BUFCOUNT/2(arrays per frame), ACNT = 4(bytes per array) writing to a (32-bit) McASP0 serialiser
*EDMA3_PaRAM_ptr++ = 0x01D02000; // destination is DMA port of McASP0
*EDMA3_PaRAM_ptr++ = 0x00000004; // dest address is static, increment source address by ACNT bytes
*EDMA3_PaRAM_ptr++ = 0x00000800; // BCNT reload value is redundant - link to PaRAM set 64
*EDMA3_PaRAM_ptr++ = 0x00000000; // CCNTIDX
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT = 1(frame per block)

// set up PaRAM set 64

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04800);

*EDMA3_PaRAM_ptr++ = 0x00000000; // same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)procptr; // apart from source buffer used
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
 
*EDMA3_PaRAM_ptr++ = 0x01D02000; 
*EDMA3_PaRAM_ptr++ = 0x00000004; 
*EDMA3_PaRAM_ptr++ = 0x00000820; // BCNT reload value is redundant - link to PaRAM set 65
*EDMA3_PaRAM_ptr++ = 0x00000000;  
*EDMA3_PaRAM_ptr++ = 0x00000001; 

// set up PaRAM set 65

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04820);

*EDMA3_PaRAM_ptr++ = 0x00000000; // exactly the same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr;
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = 0x01D02000;
*EDMA3_PaRAM_ptr++ = 0x00000004;
*EDMA3_PaRAM_ptr++ = 0x00000840; // BCNT reload value is redundant - link to PaRAM set 66
*EDMA3_PaRAM_ptr++ = 0x00000000;
*EDMA3_PaRAM_ptr++ = 0x00000001;

// set up PaRAM set 66

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04840);

*EDMA3_PaRAM_ptr++ = 0x00000000; // exactly the same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr;
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = 0x01D02000; 
*EDMA3_PaRAM_ptr++ = 0x00000004; 
*EDMA3_PaRAM_ptr++ = 0x00000800; // BCNT reload value is redundant - link to PaRAM set 64
*EDMA3_PaRAM_ptr++ = 0x00000000;  
*EDMA3_PaRAM_ptr++ = 0x00000001; 



// set up PaRAM set 0 (MCASP0 REVT)

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04000);

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT interrupt on transfer complete with TCC = 0
*EDMA3_PaRAM_ptr++ = 0x01D02000; // SRC DMA port of McASP0
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr; // DST one of two output buffers
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX increment dest by 4 bytes, src is static
*EDMA3_PaRAM_ptr++ = 0x00000860; // BCNT reload value is redundant - link to PaRAM set 67
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT 1 frame per block

// set up parameter RAM set 67

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04860);

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT similar to PaRAM set 1 but TCC = 1 and different buffer used
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x00000880; // BCNT reload value is redundant - link to PaRAM set 68
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT

// set up parameter RAM set 68

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04880); // exactly the same as PaRAM set 1

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)procptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x000008A0; // BCNT reload value is redundant - link to PaRAM set 69
*EDMA3_PaRAM_ptr++ = 0x00000000; //
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT

// set up parameter RAM set 69

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C048A0); // exactly the same as PaRAM set 1

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x00000860; // BCNT reload value is redundant - link to PaRAM set 69
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT


  EDMA_3CC_IECRH  = 0xffffffff;   // IERH - Disable high interrupts
  EDMA_3CC_EECRH  = 0xffffffff;   // EERH - Disable high events
  EDMA_3CC_ICRH   = 0xffffffff;   // ICRH - Clear high interrupts
  EDMA_3CC_ECRH   = 0xffffffff;   // ICRH - Clear high events

  EDMA_3CC_IECR   = 0xffffffff;   // IER  - Disable low interrupts
  EDMA_3CC_EECR   = 0xffffffff;   // EER  - Disable low events
  EDMA_3CC_ICR    = 0xffffffff;   // ICR  - Clear low interrupts
  EDMA_3CC_ECR    = 0xffffffff;   // ICRH - Clear low events


EDMA_3CC_EESR = 0x00000003; // enable EDMA3 events 0 and 1, i.e. McASP REVT and XEVT
}

//configure and initialise MCASP0 for edma3-based i/o
void L138_init_mcasp_edma()
{

   // reset mcasp.
   MCASP->GBLCTL  = 0;

   // configure receive registers.
   MCASP->RMASK      = 0xFFFFFFFF;
   MCASP->RFMT       = 0x000080F0;
   MCASP->AFSRCTL    = 0x00000000;
   MCASP->ACLKRCTL   = 0x00000000;
   MCASP->AHCLKRCTL  = 0x00000000;
   MCASP->RTDM       = 0x00000001; // TDM timeslot 0
   MCASP->RINTCTL    = 0x00000000;
   MCASP->RCLKCHK    = 0x00000000;

   // configure transmit registers.
   MCASP->XMASK      = 0xFFFFFFFF;
   MCASP->XFMT       = 0x000080F0;
   MCASP->AFSXCTL    = 0x00000000;
   MCASP->ACLKXCTL   = 0x00000000;
   MCASP->AHCLKXCTL  = 0x00000000;
   MCASP->XTDM       = 0x00000001; // TDM timeslot 0
   MCASP->XINTCTL    = 0x00000000;
   MCASP->XCLKCHK    = 0x00000000;

   // config serializers (13 = xmit, 14 = rcv).
   //MCASP->SRCTL7     = 0x000E;//RX from SRC4392
   //MCASP->SRCTL8     = 0x000E;//RX from PCM3168A
   //MCASP->SRCTL9     = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL10    = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL11    = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL12    = 0x000D;//TX to PCM3168A
   MCASP->SRCTL13    = 0x000D;
   MCASP->SRCTL14    = 0x000E;
   //MCASP->SRCTL15    = 0x000D;//TX to SRC4392

   // config pin function and direction.
   MCASP->PFUNC      = 0;
   MCASP->PDIR       = 0x00002000;

   //
   MCASP->DITCTL     = 0x00000000;
   MCASP->DLBCTL     = 0x00000000;
   MCASP->AMUTE      = 0x00000000;


   // enable the audio clocks, verifying each bit is properly set.
   SETBIT(MCASP->XGBLCTL, XHCLKRST);
   while (!CHKBIT(MCASP->XGBLCTL, XHCLKRST)) {}
   SETBIT(MCASP->RGBLCTL, RHCLKRST);
   while (!CHKBIT(MCASP->RGBLCTL, RHCLKRST)) {}


     EDMA3_PaRAM_setup(); //this is a key difference to L138_init_mcasp_intr()

   MCASP->XSTAT = 0x0000FFFF;        // Clear all
   MCASP->RSTAT = 0x0000FFFF;        // Clear all

// if DMA is being used, verify that the XDATA bit (5) in XSTAT
// is cleared to 0. (it should have been cleared y writing 1 to it)
   while ( ( MCASP->XSTAT & 0x00000020 ) != 0x00000000 );

   SETBIT(MCASP->XGBLCTL, XSRCLR);
   while (!CHKBIT(MCASP->XGBLCTL, XSRCLR)) {}
   SETBIT(MCASP->RGBLCTL, RSRCLR);
   while (!CHKBIT(MCASP->RGBLCTL, RSRCLR)) {}

   /* Write a 0, so that no underrun occurs after releasing the state machine */
   //MCASP->RBUF7 = 0;
   //MCASP->RBUF8 = 0;
   //MCASP->XBUF9 = 0;
   //MCASP->XBUF10 = 0;
   //MCASP->XBUF11 = 0;
   //MCASP->XBUF12 = 0;
   MCASP->XBUF13 = 0;
   MCASP->RBUF14 = 0;
   //MCASP->XBUF15 = 0;

   SETBIT(MCASP->XGBLCTL, XSMRST);
   while (!CHKBIT(MCASP->XGBLCTL, XSMRST)) {}
   SETBIT(MCASP->RGBLCTL, RSMRST);
   while (!CHKBIT(MCASP->RGBLCTL, RSMRST)) {}

   SETBIT(MCASP->XGBLCTL, XFRST);
   while (!CHKBIT(MCASP->XGBLCTL, XFRST)) {}
   SETBIT(MCASP->RGBLCTL, RFRST);
   while (!CHKBIT(MCASP->RGBLCTL, RFRST)) {}

   // wait for transmit ready and send a dummy byte.
   while(!CHKBIT(MCASP->SRCTL13, XRDY)) {}
   MCASP->XBUF13 = 0;
}


// initialise AIC3106 codec by writing to its control registers
// sampling frequency, ADC gain, and DAC attenuation are set according to parameters passed


void L138_init_aic3106_registers(int32_t fs, int16_t adc_gain, int16_t dac_atten, int8_t input_type)
{
// not every register is set here - some are left with default(reset) values
// each AIC3106 register is 8 bits wide

  AIC3106_writeRegister(  0, 0x00 );  // AIC3106_PAGESELECT is PAGE 0 REG 0
  AIC3106_writeRegister(  1, 0x80 );  // reset AIC3106 using REG 1

switch(fs) // set up sampling rate - default 8kHz
{
	case FS_8000_HZ:
	  AIC3106_writeRegister(  2, 0xAA );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_9600_HZ:
	  AIC3106_writeRegister(  2, 0x88 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_11025_HZ:
	  AIC3106_writeRegister(  2, 0x66 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_12000_HZ:
	  AIC3106_writeRegister(  2, 0x66 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_16000_HZ:
	  AIC3106_writeRegister(  2, 0x44 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_19200_HZ:
	  AIC3106_writeRegister(  2, 0x33 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_22050_HZ:
	  AIC3106_writeRegister(  2, 0x22 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_24000_HZ:
	  AIC3106_writeRegister(  2, 0x22 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_32000_HZ:
	  AIC3106_writeRegister(  2, 0x11 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_44100_HZ:
	  AIC3106_writeRegister(  2, 0x00 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_48000_HZ:
	  AIC3106_writeRegister(  2, 0x00 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	default:
	  AIC3106_writeRegister(  2, 0xAA );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
}
	  
  AIC3106_writeRegister(  3, 0x22 );  // disable PLL and set Q=4(relevant) and P=2(irrelevant)
                                      // fsref will be MCLK/(128*Q) = 48000
                                      // MCLK on eXperimenter is 24.576MHz from on-board Citizen oscillator  
  AIC3106_writeRegister(  4, 0x20 );  // J=8 (irrelevant since PLL disabled)
  AIC3106_writeRegister(  5, 0x6E );  // D=7075 MS bits (irrelevant since PLL disabled)
  AIC3106_writeRegister(  6, 0x23 );  // D=7075 LS bits (irrelevant since PLL disabled)
  AIC3106_writeRegister(  8, 0xC0 );  // Audio Interface Control A BCLK=MASTER!!!, WCLK=MASTER!!!
  AIC3106_writeRegister(  9, 0x40 );  // Audio Interface Control B DSP mode (1 slot), 32 bit slot width

  AIC3106_writeRegister( 12, 0x00 );  // Audio Interface Control C Data offset=0


  AIC3106_writeRegister( 10, 0x00 );  // Audio Interface Control C Data offset=0
// WARNING - this assumes that adc_gain is a sensible value
  AIC3106_writeRegister( 15, adc_gain );  // Left ADC Programmable Gain Amplifier Mute=OFF Gain=0dB
  AIC3106_writeRegister( 16, adc_gain );  // Right ADC Programmable Gain Amplifier Mute=OFF Gain=0dB

  if (input_type == LCDK_LINE_INPUT)
  {
    AIC3106_writeRegister( 19, 0x04 );  // power up ADCs
    AIC3106_writeRegister( 22, 0x04 );  // and connect LINE1L/R to ADC
  }
  else
  {
    AIC3106_writeRegister( 19, 0x7C );  // power up ADCs
    AIC3106_writeRegister( 22, 0x7C );  // and do not connect LINE1L/R to ADC
    AIC3106_writeRegister( 17, 0x0F );  // 17 MIC3L to L ADC (default 0xFF, NC) 0x00 0dB
    AIC3106_writeRegister( 18, 0xF0 );  // 18 MIC3R to R ADC (default 0xFF, NC) 0x00 0dB
    AIC3106_writeRegister( 25, 0x40 );  // 25 MICBIAS 0x40 2V, 0x00 OFF
  }

  AIC3106_writeRegister( 37, 0xE0 );  // DAC Power & Output Dvr LeftDAC=ON, RightDAC=ON, HPLCOM=SingleEnd]
// WARNING - this assumes that dac_atten is a sensible value
  AIC3106_writeRegister( 43, dac_atten );  // Left DAC Digital Volume Mute=OFF, Gain=0dB
  AIC3106_writeRegister( 44, dac_atten );  // Right DAC Digital Volume Mute=OFF, Gain=0dB
  AIC3106_writeRegister( 82, 0x80 );  // was 0x80 DAC_L1 to LEFT_LOP/M Volume Routed, Gain=0dB
  AIC3106_writeRegister( 86, 0x09 );  // LEFT_LOP/M Output Mute=OFF bit3 bit0 is REad only ?! must be set!
  AIC3106_writeRegister( 92, 0x80 );  // was 0x80 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
  AIC3106_writeRegister( 93, 0x09 );  // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
  AIC3106_writeRegister( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
  AIC3106_writeRegister( 102, 0 );
}

void L138_init_pcm3168a_registers(void)
{
	PCM3168A_writeRegister( 64, 0x00 );//sets registers to default
	//look into quad rate sampling set up above
	PCM3168A_writeRegister( 65, 0x83 );//power save disabled, slave mode, 16-bit right-justified format
	PCM3168A_writeRegister( 66, 0x00 );//all DACs enabled, all DACs sharp rolloff
	PCM3168A_writeRegister( 67, 0x00 );//all DACs normal phase select
	PCM3168A_writeRegister( 68, 0x00 );//all DACs mute disabled
	//register 69 zero input flags read only
	PCM3168A_writeRegister( 70, 0x00 );//independant DAC attenuation, fast attenuation speed, de-emphasis disabled,ZERO output pin uses 8 channel AND logic, pin goes high for zero detect
	PCM3168A_writeRegister( 71, 0xFF );//No DAC attenuation for master attenuator
	PCM3168A_writeRegister( 72, 0xFF );//No DAC attenuation DAC1
	PCM3168A_writeRegister( 73, 0xFF );//No DAC attenuation DAC2
	PCM3168A_writeRegister( 74, 0xFF );//No DAC attenuation DAC3
	PCM3168A_writeRegister( 75, 0xFF );//No DAC attenuation DAC4
	PCM3168A_writeRegister( 76, 0xFF );//No DAC attenuation DAC5
	PCM3168A_writeRegister( 77, 0xFF );//No DAC attenuation DAC6
	PCM3168A_writeRegister( 78, 0xFF );//No DAC attenuation DAC7
	PCM3168A_writeRegister( 79, 0xFF );//No DAC attenuation DAC8

	PCM3168A_writeRegister( 80, 0x00 );//ADC sample rate select set to AUTO
	//look into dual rate sampling set up above
	PCM3168A_writeRegister( 81, 0x03 );//ADC slave mode, 16-bit right-justified format
	PCM3168A_writeRegister( 82, 0x60 );//ADC 1/2 normal, 3/4/5/6 disabled, ADC HPF enabled all channels to remove DC
	PCM3168A_writeRegister( 83, 0x00 );//all ADC channels differential input
	PCM3168A_writeRegister( 84, 0x00 );//all ADC inputs normal phase
	PCM3168A_writeRegister( 85, 0x00 );//all ADCs mute disabled
	//register 86 input overflow flags read only
	PCM3168A_writeRegister( 87, 0x00 );//independant ADC channel attenuation, fast attenuation speed, overflow pin goes high on overflow
	PCM3168A_writeRegister( 88, 0xD7 );//No ADC attenuation/gain for master attenuator
	PCM3168A_writeRegister( 89, 0xD7 );//No ADC attenuation/gain for ADC1
	PCM3168A_writeRegister( 90, 0xD7 );//No ADC attenuation/gain for ADC2
	PCM3168A_writeRegister( 91, 0xD7 );//No ADC attenuation/gain for ADC3
	PCM3168A_writeRegister( 92, 0xD7 );//No ADC attenuation/gain for ADC4
	PCM3168A_writeRegister( 93, 0xD7 );//No ADC attenuation/gain for ADC5
	PCM3168A_writeRegister( 94, 0xD7 );//No ADC attenuation/gain for ADC6
}




void L138_init_src4392_registers(void)
{
	SRC4392_writeRegister( 0x7F, 0x00);//set current register page to page Zero
	SRC4392_writeRegister( 0x01, 0x80);//reset all registers to default values
	SRC4392_writeRegister( 0x7F, 0x00);//set current register page to page Zero
	SRC4392_writeRegister( 0x01, 0x37);//SRC enabled, RX enabled, TX enabled, PORTB disabled, PORTA enabled, power down all functions disabled, reset disbaled

	//Register 02: Global Interrupt Status (Read-Only)

	SRC4392_writeRegister( 0x03, 0x34);//port A set to 16 bit, slave mode, port A output from SRC, output mute disabled

	//Register 04: Port A Control Register 2 PORT A SLAVE MODE
	//Register 05: Port B Control Register 1 PORT B DISABLED
	//Register 06: Port B Control Register 2 PORT B DISABLED

	SRC4392_writeRegister( 0x07, 0x60 );//TX master clock divider is 512, TX masted clock source is MCLK
	SRC4392_writeRegister( 0x08, 0x00 );//TX+ and TX- enabled, TX mute disabled,
	SRC4392_writeRegister( 0x09, 0x00 );//
	//Register 0A: SRC and DIT Status (Read-Only)
	SRC4392_writeRegister( 0x0B, 0x00 );//DIT and SRC interrupts all masked
	SRC4392_writeRegister( 0x0C, 0x00 );//DIT and SRC interrupts all masked

	SRC4392_writeRegister( 0x0D, 0x08 );//Receiver input 1 (optical) is selected, RX clock is MCLK, Receiver C and U Data Buffer Transfer update as usual
	SRC4392_writeRegister( 0x0E, 0x00);//RXCKOE Output disabled, RXCKO not divided, Receiver Automatic Mute for Loss of Lock disabled, PLL2 output clock is stopped for a loss of lock
	SRC4392_writeRegister( 0x0F, 0x22);//set RX clock for 48kHz from 24.576 MCLK
	SRC4392_writeRegister( 0x10, 0x00);//set RX clock for 48kHz from 24.576 MCLK
	SRC4392_writeRegister( 0x11, 0x00);//set RX clock for 48kHz from 24.576 MCLK

	//Register 12: Non-PCM Audio Detection Status Register (Read-Only)
	//Register 13: Receiver Status Register 1 (Read-Only)
	//Register 14: Receiver Status Register 2 (Read-Only)
	//Register 15: Receiver Status Register 3 (Read-Only)

	SRC4392_writeRegister( 0x16, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x17, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x18, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x19, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x1A, 0x00);//RX interrupts all masked

	SRC4392_writeRegister( 0x1B, 0x01);//GPIO1 forced HIGH
	SRC4392_writeRegister( 0x1C, 0x01);//GPIO2 forced HIGH
	SRC4392_writeRegister( 0x1D, 0x01);//GPIO3 forced HIGH
	SRC4392_writeRegister( 0x1E, 0x01);//GPIO4 forced HIGH

	//Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address
	//Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track
	//Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index
	//Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes
	//Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds
	//Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame
	//Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero
	//Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN
	//Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC
	//Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME
	//Register 29: Burst Preamble PC High-Byte Status Register (Read-Only)
	//Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only)
	//Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only)
	//Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)

	SRC4392_writeRegister( 0x2D, 0x42);//SRC input is DIR, SRC reference clock is MCLK, SRC output mute disabled, left and right attenuation tracking enabled
	SRC4392_writeRegister( 0x2E, 0x20);//interpolation filter buffers 64 samples, decimation filter enabled, manual de-emphasis disabled, auto de-emphasis enabled
	SRC4392_writeRegister( 0x2F, 0xC0);//SRC output word is 16 bits
	SRC4392_writeRegister( 0x30, 0x00);//Left channel attenuation set to 0
	SRC4392_writeRegister( 0x31, 0x00);//Right channel attenuation was previously set to track left channel

	//Register 32: SRC Ratio Readback Register (Read-Only)
	//Register 33: SRC Ratio Readback Register (Read-Only)
}

/*
void L138_init_LCDK_DIP()
{
  GPIO_setDir(GPIO_BANK0, GPIO_PIN1, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN2, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN3, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN4, GPIO_INPUT);
  return;
}

uint8_t read_LCDK_user_DIP()
{
  uint8_t DIP_1, DIP_2, DIP_3, DIP_4;

  GPIO_getInput(GPIO_BANK0, GPIO_PIN4, &DIP_4);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN3, &DIP_3);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN2, &DIP_2);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN1, &DIP_1);
  return((uint8_t)(DIP_1 + 2*DIP_2 + 4*DIP_3 + 8*DIP_4));
}
/*/

// initialisation routine called by example program for edma3-based i/o
void L138_initialise_edma(int32_t fs, int16_t adc_gain, int16_t dac_atten, int8_t input_type)
{
  poll = 0;     // used in input_sample() and output_sample() functions
  // allocate memory for ping pong buffers
  outptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  inptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  procptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  USTIMER_init();

  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_0, PINMUX_MCASP_MASK_0, PINMUX_MCASP_VAL_0);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_1, PINMUX_MCASP_MASK_1, PINMUX_MCASP_VAL_1);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_2, PINMUX_MCASP_MASK_2, PINMUX_MCASP_VAL_2);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_4, PINMUX_MCASP_MASK_4, PINMUX_MCASP_VAL_4);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_5, PINMUX_MCASP_MASK_5, PINMUX_MCASP_VAL_5);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_10, PINMUX_MCASP_MASK_10, PINMUX_MCASP_VAL_10);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_11, PINMUX_MCASP_MASK_11, PINMUX_MCASP_VAL_11);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_18, PINMUX_MCASP_MASK_18, PINMUX_MCASP_VAL_18);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_19, PINMUX_MCASP_MASK_19, PINMUX_MCASP_VAL_19);

  // replaces I2C_init();
  *( volatile uint32_t* )(0x01C22024) = 0;
  *( volatile uint32_t* )(0x01C22030) = 2;
  *( volatile uint32_t* )(0x01C2200C) = 5;
  *( volatile uint32_t* )(0x01C22010) = 5;
  *( volatile uint32_t* )(0x01C22024) |= 0x20;
 
  CSR = 0x0000; // disable interrupts globally while initialising
                // GIE is bit 0 of CSR register

  L138_init_aic3106_registers(fs, adc_gain, dac_atten,input_type);
  L138_init_pcm3168a_registers();
  L138_init_src4392_registers();

  L138_init_mcasp_edma();

  // clear any pending interrupts within EDMA3CC
  EDMA_3CC_ICR = 0x0007; // writing to ICR affects IPR
  // associate event n with interrupt 4 by writing n into LSBs of INTMUX1
  // LSBs of INTMUX1 are literally associated with INT4
  // in this case n=8 (EDMA3CC   event)
  INTC_INTMUX1 = 0x00000008;

  ISTP = (unsigned int)vectors;
  // enable TCC = 0 and TCC = 1 EDMA3 interrupts by setting bits 0 and 1 in IESR
  EDMA3_IESR = 0x0003;
  EDMA3_DRAE1 = 0x0003;

  // clear all pending interrupt flags
  // interrupt clear register ICR is used to clear bits in interrupt flag register IFR
  ICR = 0xFFF0;  // ICR bits 3, 2, 1, and 0 are reserved, read as 0, write has no effect
  IER |= 0x12;  //enable NMI (bit 1) and INT4 (bit 4)
  
  CSR |= 0x01;  // enable interrupts globally
  //L138_init_LCDK_DIP();

}

My goal is the use a digital input from the src4392 and 8 outputs from the PCM3168A so I will set the PCM33168A as master.

I have verified I can connect to the the PCM3168A and SRC4392 and configure them with I2C bus as planned.

I have done this and I have checked the PCM3168A is generating the WCLK and BCLK signals which are ok (48kHz and 3.072Mhz ). Here is the code to this point:

// L138_LCDK_aic3106_init.c
//
// triple buffer edma version

#include "L138_LCDK_aic3106_init_triple.h"

int16_t *tempptr, *inptr, *outptr, *procptr;

int16_t *aic3106_input_A, *aic3106_input_B;
int16_t *aic3106_output_A, *aic3106_output_B;

int16_t *analog_input_A, *analog_input_B;

int16_t *digital_input_A, *digital_input_B;

int16_t *analog_output_1_2_A, *analog_output_1_2_B, *analog_output_3_4_A, *analog_output_3_4_B;
int16_t *analog_output_5_6_A, *analog_output_5_6_B, *analog_output_7_8_A, *analog_output_7_8_B;

int16_t *digital_output_A, *digital_output_B;

extern void vectors(void);


void EDMA3_PaRAM_setup() // sets up PaRAM and enables EDMA events
{
uint32_t *EDMA3_PaRAM_ptr;
// PaRAM sets (channels) 0 and 1, triggered by McASP0
// receive and transmit events respectively, are used
// with linked parameters set up in PaRAM sets (channels) 64, 65, 67, and 68
// the linked parameters differ only in the ping or pong buffers used

// set up PaRAM set 1 (MCASP0 XEVT)

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04020);

*EDMA3_PaRAM_ptr++ = 0x00000000; // no EDMA3 interrupts on transfer complete
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr; // source is one of two output buffers
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
// BCNT = BUFCOUNT/2(arrays per frame), ACNT = 4(bytes per array) writing to a (32-bit) McASP0 serialiser
*EDMA3_PaRAM_ptr++ = 0x01D02000; // destination is DMA port of McASP0
*EDMA3_PaRAM_ptr++ = 0x00000004; // dest address is static, increment source address by ACNT bytes
*EDMA3_PaRAM_ptr++ = 0x00000800; // BCNT reload value is redundant - link to PaRAM set 64
*EDMA3_PaRAM_ptr++ = 0x00000000; // CCNTIDX
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT = 1(frame per block)

// set up PaRAM set 64

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04800);

*EDMA3_PaRAM_ptr++ = 0x00000000; // same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)procptr; // apart from source buffer used
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
 
*EDMA3_PaRAM_ptr++ = 0x01D02000; 
*EDMA3_PaRAM_ptr++ = 0x00000004; 
*EDMA3_PaRAM_ptr++ = 0x00000820; // BCNT reload value is redundant - link to PaRAM set 65
*EDMA3_PaRAM_ptr++ = 0x00000000;  
*EDMA3_PaRAM_ptr++ = 0x00000001; 

// set up PaRAM set 65

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04820);

*EDMA3_PaRAM_ptr++ = 0x00000000; // exactly the same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr;
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = 0x01D02000;
*EDMA3_PaRAM_ptr++ = 0x00000004;
*EDMA3_PaRAM_ptr++ = 0x00000840; // BCNT reload value is redundant - link to PaRAM set 66
*EDMA3_PaRAM_ptr++ = 0x00000000;
*EDMA3_PaRAM_ptr++ = 0x00000001;

// set up PaRAM set 66

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04840);

*EDMA3_PaRAM_ptr++ = 0x00000000; // exactly the same as PaRAM set 1
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr;
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = 0x01D02000; 
*EDMA3_PaRAM_ptr++ = 0x00000004; 
*EDMA3_PaRAM_ptr++ = 0x00000800; // BCNT reload value is redundant - link to PaRAM set 64
*EDMA3_PaRAM_ptr++ = 0x00000000;  
*EDMA3_PaRAM_ptr++ = 0x00000001; 



// set up PaRAM set 0 (MCASP0 REVT)

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04000);

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT interrupt on transfer complete with TCC = 0
*EDMA3_PaRAM_ptr++ = 0x01D02000; // SRC DMA port of McASP0
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr; // DST one of two output buffers
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX increment dest by 4 bytes, src is static
*EDMA3_PaRAM_ptr++ = 0x00000860; // BCNT reload value is redundant - link to PaRAM set 67
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT 1 frame per block

// set up parameter RAM set 67

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04860);

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT similar to PaRAM set 1 but TCC = 1 and different buffer used
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)outptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x00000880; // BCNT reload value is redundant - link to PaRAM set 68
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT

// set up parameter RAM set 68

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C04880); // exactly the same as PaRAM set 1

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)procptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x000008A0; // BCNT reload value is redundant - link to PaRAM set 69
*EDMA3_PaRAM_ptr++ = 0x00000000; //
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT

// set up parameter RAM set 69

EDMA3_PaRAM_ptr = (unsigned int *)(0x01C048A0); // exactly the same as PaRAM set 1

*EDMA3_PaRAM_ptr++ = 0x00100000; // OPT
*EDMA3_PaRAM_ptr++ = 0x01D02000;    // SRC
*EDMA3_PaRAM_ptr++ = (int32_t)((((BUFCOUNT/2)<<16) & 0xFFFF0000) | 0x00000004);
*EDMA3_PaRAM_ptr++ = (unsigned int)inptr; // DST - single address used for XBUFn, RBUFn if RBSEL = 0
*EDMA3_PaRAM_ptr++ = 0x00040000; // DSTBIDX, SRCBIDX
*EDMA3_PaRAM_ptr++ = 0x00000860; // BCNT reload value is redundant - link to PaRAM set 69
*EDMA3_PaRAM_ptr++ = 0x00000000; // 
*EDMA3_PaRAM_ptr++ = 0x00000001; // rsvd, CCNT


  EDMA_3CC_IECRH  = 0xffffffff;   // IERH - Disable high interrupts
  EDMA_3CC_EECRH  = 0xffffffff;   // EERH - Disable high events
  EDMA_3CC_ICRH   = 0xffffffff;   // ICRH - Clear high interrupts
  EDMA_3CC_ECRH   = 0xffffffff;   // ICRH - Clear high events

  EDMA_3CC_IECR   = 0xffffffff;   // IER  - Disable low interrupts
  EDMA_3CC_EECR   = 0xffffffff;   // EER  - Disable low events
  EDMA_3CC_ICR    = 0xffffffff;   // ICR  - Clear low interrupts
  EDMA_3CC_ECR    = 0xffffffff;   // ICRH - Clear low events


EDMA_3CC_EESR = 0x00000003; // enable EDMA3 events 0 and 1, i.e. McASP REVT and XEVT
}

//configure and initialise MCASP0 for edma3-based i/o
void L138_init_mcasp_edma()
{

   // reset mcasp.
   MCASP->GBLCTL  = 0;

   // configure receive registers.
   MCASP->RMASK      = 0xFFFFFFFF;
   MCASP->RFMT       = 0x000080F0;
   MCASP->AFSRCTL    = 0x00000000;
   MCASP->ACLKRCTL   = 0x00000000;
   MCASP->AHCLKRCTL  = 0x00000000;
   MCASP->RTDM       = 0x00000001; // TDM timeslot 0
   MCASP->RINTCTL    = 0x00000000;
   MCASP->RCLKCHK    = 0x00000000;

   // configure transmit registers.
   MCASP->XMASK      = 0xFFFFFFFF;
   MCASP->XFMT       = 0x000080F0;
   MCASP->AFSXCTL    = 0x00000000;
   MCASP->ACLKXCTL   = 0x00000000;
   MCASP->AHCLKXCTL  = 0x00000000;
   MCASP->XTDM       = 0x00000001; // TDM timeslot 0
   MCASP->XINTCTL    = 0x00000000;
   MCASP->XCLKCHK    = 0x00000000;

   // config serializers (13 = xmit, 14 = rcv).
   //MCASP->SRCTL7     = 0x000E;//RX from SRC4392
   MCASP->SRCTL8     = 0x000E;//RX from PCM3168A            //Swapped SRCTL8 for SRCTL14
   MCASP->SRCTL9     = 0x000D;//TX to PCM3168A              //Swapped SRCTL9 for SRCTL13
   //MCASP->SRCTL10    = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL11    = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL12    = 0x000D;//TX to PCM3168A
   //MCASP->SRCTL13    = 0x000D;
   //MCASP->SRCTL14    = 0x000E;
   //MCASP->SRCTL15    = 0x000D;//TX to SRC4392

   // config pin function and direction.
   MCASP->PFUNC      = 0;
   MCASP->PDIR       = 0x00000200;                          //Swapped SRCTL9 for SRCTL13 as transmitter

   //
   MCASP->DITCTL     = 0x00000000;
   MCASP->DLBCTL     = 0x00000000;
   MCASP->AMUTE      = 0x00000000;


   // enable the audio clocks, verifying each bit is properly set.
   SETBIT(MCASP->XGBLCTL, XHCLKRST);
   while (!CHKBIT(MCASP->XGBLCTL, XHCLKRST)) {}
   SETBIT(MCASP->RGBLCTL, RHCLKRST);
   while (!CHKBIT(MCASP->RGBLCTL, RHCLKRST)) {}


     EDMA3_PaRAM_setup(); //this is a key difference to L138_init_mcasp_intr()

   MCASP->XSTAT = 0x0000FFFF;        // Clear all
   MCASP->RSTAT = 0x0000FFFF;        // Clear all

// if DMA is being used, verify that the XDATA bit (5) in XSTAT
// is cleared to 0. (it should have been cleared y writing 1 to it)
   while ( ( MCASP->XSTAT & 0x00000020 ) != 0x00000000 );

   SETBIT(MCASP->XGBLCTL, XSRCLR);
   while (!CHKBIT(MCASP->XGBLCTL, XSRCLR)) {}
   SETBIT(MCASP->RGBLCTL, RSRCLR);
   while (!CHKBIT(MCASP->RGBLCTL, RSRCLR)) {}

   /* Write a 0, so that no underrun occurs after releasing the state machine */
   //MCASP->RBUF7 = 0;
   MCASP->RBUF8 = 0;
   MCASP->XBUF9 = 0;
   //MCASP->XBUF10 = 0;
   //MCASP->XBUF11 = 0;
   //MCASP->XBUF12 = 0;
   //MCASP->XBUF13 = 0;
   //MCASP->RBUF14 = 0;
   //MCASP->XBUF15 = 0;

   SETBIT(MCASP->XGBLCTL, XSMRST);
   while (!CHKBIT(MCASP->XGBLCTL, XSMRST)) {}
   SETBIT(MCASP->RGBLCTL, RSMRST);
   while (!CHKBIT(MCASP->RGBLCTL, RSMRST)) {}

   SETBIT(MCASP->XGBLCTL, XFRST);
   while (!CHKBIT(MCASP->XGBLCTL, XFRST)) {}
   SETBIT(MCASP->RGBLCTL, RFRST);
   while (!CHKBIT(MCASP->RGBLCTL, RFRST)) {}

   // wait for transmit ready and send a dummy byte.
   while(!CHKBIT(MCASP->SRCTL9, XRDY)) {}                           //Swapped SRCTL9 for SRCTL13. After this swap, code gets stuck here
   MCASP->XBUF9 = 0;                                                //Swapped SRCTL9 for SRCTL13
}


// initialise AIC3106 codec by writing to its control registers
// sampling frequency, ADC gain, and DAC attenuation are set according to parameters passed


void L138_init_aic3106_registers(int32_t fs, int16_t adc_gain, int16_t dac_atten, int8_t input_type)
{
// not every register is set here - some are left with default(reset) values
// each AIC3106 register is 8 bits wide

  AIC3106_writeRegister(  0, 0x00 );  // AIC3106_PAGESELECT is PAGE 0 REG 0
  AIC3106_writeRegister(  1, 0x80 );  // reset AIC3106 using REG 1

switch(fs) // set up sampling rate - default 8kHz
{
	case FS_8000_HZ:
	  AIC3106_writeRegister(  2, 0xAA );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_9600_HZ:
	  AIC3106_writeRegister(  2, 0x88 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_11025_HZ:
	  AIC3106_writeRegister(  2, 0x66 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_12000_HZ:
	  AIC3106_writeRegister(  2, 0x66 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_16000_HZ:
	  AIC3106_writeRegister(  2, 0x44 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_19200_HZ:
	  AIC3106_writeRegister(  2, 0x33 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_22050_HZ:
	  AIC3106_writeRegister(  2, 0x22 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_24000_HZ:
	  AIC3106_writeRegister(  2, 0x22 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_32000_HZ:
	  AIC3106_writeRegister(  2, 0x11 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_44100_HZ:
	  AIC3106_writeRegister(  2, 0x00 );
      AIC3106_writeRegister(  7, 0x8A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	case FS_48000_HZ:
	  AIC3106_writeRegister(  2, 0x00 );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
	default:
	  AIC3106_writeRegister(  2, 0xAA );
      AIC3106_writeRegister(  7, 0x0A );  // Codec Datapath Setup [LeftDAC=LEFT][RightDAC=RIGHT]
	  break;
}
	  
  AIC3106_writeRegister(  3, 0x22 );  // disable PLL and set Q=4(relevant) and P=2(irrelevant)
                                      // fsref will be MCLK/(128*Q) = 48000
                                      // MCLK on eXperimenter is 24.576MHz from on-board Citizen oscillator  
  AIC3106_writeRegister(  4, 0x20 );  // J=8 (irrelevant since PLL disabled)
  AIC3106_writeRegister(  5, 0x6E );  // D=7075 MS bits (irrelevant since PLL disabled)
  AIC3106_writeRegister(  6, 0x23 );  // D=7075 LS bits (irrelevant since PLL disabled)
  AIC3106_writeRegister(  8, 0x00 );  // Audio Interface Control A BCLK=SLAVE!!!, WCLK=SLAVE!!!
  AIC3106_writeRegister(  9, 0x40 );  // Audio Interface Control B DSP mode (1 slot), 32 bit slot width

  AIC3106_writeRegister( 12, 0x00 );  // Audio Interface Control C Data offset=0


  AIC3106_writeRegister( 10, 0x00 );  // Audio Interface Control C Data offset=0
// WARNING - this assumes that adc_gain is a sensible value
  AIC3106_writeRegister( 15, adc_gain );  // Left ADC Programmable Gain Amplifier Mute=OFF Gain=0dB
  AIC3106_writeRegister( 16, adc_gain );  // Right ADC Programmable Gain Amplifier Mute=OFF Gain=0dB

  if (input_type == LCDK_LINE_INPUT)
  {
    AIC3106_writeRegister( 19, 0x04 );  // power up ADCs
    AIC3106_writeRegister( 22, 0x04 );  // and connect LINE1L/R to ADC
  }
  else
  {
    AIC3106_writeRegister( 19, 0x7C );  // power up ADCs
    AIC3106_writeRegister( 22, 0x7C );  // and do not connect LINE1L/R to ADC
    AIC3106_writeRegister( 17, 0x0F );  // 17 MIC3L to L ADC (default 0xFF, NC) 0x00 0dB
    AIC3106_writeRegister( 18, 0xF0 );  // 18 MIC3R to R ADC (default 0xFF, NC) 0x00 0dB
    AIC3106_writeRegister( 25, 0x40 );  // 25 MICBIAS 0x40 2V, 0x00 OFF
  }

  AIC3106_writeRegister( 37, 0xE0 );  // DAC Power & Output Dvr LeftDAC=ON, RightDAC=ON, HPLCOM=SingleEnd]
// WARNING - this assumes that dac_atten is a sensible value
  AIC3106_writeRegister( 43, dac_atten );  // Left DAC Digital Volume Mute=OFF, Gain=0dB
  AIC3106_writeRegister( 44, dac_atten );  // Right DAC Digital Volume Mute=OFF, Gain=0dB
  AIC3106_writeRegister( 82, 0x80 );  // was 0x80 DAC_L1 to LEFT_LOP/M Volume Routed, Gain=0dB
  AIC3106_writeRegister( 86, 0x09 );  // LEFT_LOP/M Output Mute=OFF bit3 bit0 is REad only ?! must be set!
  AIC3106_writeRegister( 92, 0x80 );  // was 0x80 92 DAC_R1 to RIGHT_LOP/M Volume    <- [Routed]
  AIC3106_writeRegister( 93, 0x09 );  // 93           RIGHT_LOP/M Output    <- [Mute=OFF][Power=ON]
  AIC3106_writeRegister( 101, 0x01 ); // 101 GPIO Control Register B        <- [CODEC_CLKIN = CLKDIV_OUT]
  AIC3106_writeRegister( 102, 0 );
}

void L138_init_pcm3168a_registers(void)
{
	PCM3168A_writeRegister( 64, 0x00 );//sets registers to default
	//look into quad rate sampling set up above
	PCM3168A_writeRegister( 65, 0xA3 );//power save disabled, MASTER mode, 16-bit right-justified format    //MODIFIED
	PCM3168A_writeRegister( 66, 0x00 );//all DACs enabled, all DACs sharp rolloff
	PCM3168A_writeRegister( 67, 0x00 );//all DACs normal phase select
	PCM3168A_writeRegister( 68, 0x00 );//all DACs mute disabled
	//register 69 zero input flags read only
	PCM3168A_writeRegister( 70, 0x00 );//independant DAC attenuation, fast attenuation speed, de-emphasis disabled,ZERO output pin uses 8 channel AND logic, pin goes high for zero detect
	PCM3168A_writeRegister( 71, 0xFF );//No DAC attenuation for master attenuator
	PCM3168A_writeRegister( 72, 0xFF );//No DAC attenuation DAC1
	PCM3168A_writeRegister( 73, 0xFF );//No DAC attenuation DAC2
	PCM3168A_writeRegister( 74, 0xFF );//No DAC attenuation DAC3
	PCM3168A_writeRegister( 75, 0xFF );//No DAC attenuation DAC4
	PCM3168A_writeRegister( 76, 0xFF );//No DAC attenuation DAC5
	PCM3168A_writeRegister( 77, 0xFF );//No DAC attenuation DAC6
	PCM3168A_writeRegister( 78, 0xFF );//No DAC attenuation DAC7
	PCM3168A_writeRegister( 79, 0xFF );//No DAC attenuation DAC8

	PCM3168A_writeRegister( 80, 0x00 );//ADC sample rate select set to AUTO
	//look into dual rate sampling set up above
	PCM3168A_writeRegister( 81, 0x03 );//ADC slave mode, 16-bit right-justified format
	PCM3168A_writeRegister( 82, 0x60 );//ADC 1/2 normal, 3/4/5/6 disabled, ADC HPF enabled all channels to remove DC
	PCM3168A_writeRegister( 83, 0x00 );//all ADC channels differential input
	PCM3168A_writeRegister( 84, 0x00 );//all ADC inputs normal phase
	PCM3168A_writeRegister( 85, 0x00 );//all ADCs mute disabled
	//register 86 input overflow flags read only
	PCM3168A_writeRegister( 87, 0x00 );//independant ADC channel attenuation, fast attenuation speed, overflow pin goes high on overflow
	PCM3168A_writeRegister( 88, 0xD7 );//No ADC attenuation/gain for master attenuator
	PCM3168A_writeRegister( 89, 0xD7 );//No ADC attenuation/gain for ADC1
	PCM3168A_writeRegister( 90, 0xD7 );//No ADC attenuation/gain for ADC2
	PCM3168A_writeRegister( 91, 0xD7 );//No ADC attenuation/gain for ADC3
	PCM3168A_writeRegister( 92, 0xD7 );//No ADC attenuation/gain for ADC4
	PCM3168A_writeRegister( 93, 0xD7 );//No ADC attenuation/gain for ADC5
	PCM3168A_writeRegister( 94, 0xD7 );//No ADC attenuation/gain for ADC6
}




void L138_init_src4392_registers(void)
{
	SRC4392_writeRegister( 0x7F, 0x00);//set current register page to page Zero
	SRC4392_writeRegister( 0x01, 0x80);//reset all registers to default values
	SRC4392_writeRegister( 0x7F, 0x00);//set current register page to page Zero
	SRC4392_writeRegister( 0x01, 0x37);//SRC enabled, RX enabled, TX enabled, PORTB disabled, PORTA enabled, power down all functions disabled, reset disbaled

	//Register 02: Global Interrupt Status (Read-Only)

	SRC4392_writeRegister( 0x03, 0x34);//port A set to 16 bit, slave mode, port A output from SRC, output mute disabled

	//Register 04: Port A Control Register 2 PORT A SLAVE MODE
	//Register 05: Port B Control Register 1 PORT B DISABLED
	//Register 06: Port B Control Register 2 PORT B DISABLED

	SRC4392_writeRegister( 0x07, 0x60 );//TX master clock divider is 512, TX master clock source is MCLK
	SRC4392_writeRegister( 0x08, 0x00 );//TX+ and TX- enabled, TX mute disabled,
	SRC4392_writeRegister( 0x09, 0x00 );//
	//Register 0A: SRC and DIT Status (Read-Only)
	SRC4392_writeRegister( 0x0B, 0x00 );//DIT and SRC interrupts all masked
	SRC4392_writeRegister( 0x0C, 0x00 );//DIT and SRC interrupts all masked

	SRC4392_writeRegister( 0x0D, 0x08 );//Receiver input 1 (optical) is selected, RX clock is MCLK, Receiver C and U Data Buffer Transfer update as usual
	SRC4392_writeRegister( 0x0E, 0x00);//RXCKOE Output disabled, RXCKO not divided, Receiver Automatic Mute for Loss of Lock disabled, PLL2 output clock is stopped for a loss of lock
	SRC4392_writeRegister( 0x0F, 0x22);//set RX clock for 48kHz from 24.576 MCLK
	SRC4392_writeRegister( 0x10, 0x00);//set RX clock for 48kHz from 24.576 MCLK
	SRC4392_writeRegister( 0x11, 0x00);//set RX clock for 48kHz from 24.576 MCLK

	//Register 12: Non-PCM Audio Detection Status Register (Read-Only)
	//Register 13: Receiver Status Register 1 (Read-Only)
	//Register 14: Receiver Status Register 2 (Read-Only)
	//Register 15: Receiver Status Register 3 (Read-Only)

	SRC4392_writeRegister( 0x16, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x17, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x18, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x19, 0x00);//RX interrupts all masked
	SRC4392_writeRegister( 0x1A, 0x00);//RX interrupts all masked

	SRC4392_writeRegister( 0x1B, 0x01);//GPIO1 forced HIGH
	SRC4392_writeRegister( 0x1C, 0x01);//GPIO2 forced HIGH
	SRC4392_writeRegister( 0x1D, 0x01);//GPIO3 forced HIGH
	SRC4392_writeRegister( 0x1E, 0x01);//GPIO4 forced HIGH

	//Register 1F: Q-Channel Sub-Code Data Register 1 (Read-Only), Bits[7:0], Control and Address
	//Register 20: Q-Channel Sub-Code Data Register 2 (Read-Only), Bits[15:8], Track
	//Register 21: Q-Channel Sub-Code Data Register 3 (Read-Only), Bits[23:16], Index
	//Register 22: Q-Channel Sub-Code Data Register 4 (Read-Only), Bits[31:24], Minutes
	//Register 23: : Q-Channel Sub-Code Data Register 5 (Read-Only), Bits[39:32], Seconds
	//Register 24: : Q-Channel Sub-Code Data Register 6 (Read-Only), Bits[47:40], Frame
	//Register 25: Q-Channel Sub-Code Data Register 7 (Read-Only), Bits[55:48], Zero
	//Register 26: Q-Channel Sub-Code Data Register 8 (Read-Only), Bits[63:56], AMIN
	//Register 27: Q-Channel Sub-Code Data Register 9 (Read-Only), Bits[71:64], ASEC
	//Register 28: Q-Channel Sub-Code Data Register 10 (Read-Only), Bits[79:72], AFRAME
	//Register 29: Burst Preamble PC High-Byte Status Register (Read-Only)
	//Register 2A: Burst Preamble PC Low-Byte Status Register (Read-Only)
	//Register 2B: Burst Preamble PD High-Byte Status Register (Read-Only)
	//Register 2C: Burst Preamble PD Low-Byte Status Register (Read-Only)

	SRC4392_writeRegister( 0x2D, 0x42);//SRC input is DIR, SRC reference clock is MCLK, SRC output mute disabled, left and right attenuation tracking enabled
	SRC4392_writeRegister( 0x2E, 0x20);//interpolation filter buffers 64 samples, decimation filter enabled, manual de-emphasis disabled, auto de-emphasis enabled
	SRC4392_writeRegister( 0x2F, 0xC0);//SRC output word is 16 bits
	SRC4392_writeRegister( 0x30, 0x00);//Left channel attenuation set to 0
	SRC4392_writeRegister( 0x31, 0x00);//Right channel attenuation was previously set to track left channel

	//Register 32: SRC Ratio Readback Register (Read-Only)
	//Register 33: SRC Ratio Readback Register (Read-Only)
}

/*
void L138_init_LCDK_DIP()
{
  GPIO_setDir(GPIO_BANK0, GPIO_PIN1, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN2, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN3, GPIO_INPUT);
  GPIO_setDir(GPIO_BANK0, GPIO_PIN4, GPIO_INPUT);
  return;
}

uint8_t read_LCDK_user_DIP()
{
  uint8_t DIP_1, DIP_2, DIP_3, DIP_4;

  GPIO_getInput(GPIO_BANK0, GPIO_PIN4, &DIP_4);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN3, &DIP_3);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN2, &DIP_2);
  GPIO_getInput(GPIO_BANK0, GPIO_PIN1, &DIP_1);
  return((uint8_t)(DIP_1 + 2*DIP_2 + 4*DIP_3 + 8*DIP_4));
}
/*/

// initialisation routine called by example program for edma3-based i/o
void L138_initialise_edma(int32_t fs, int16_t adc_gain, int16_t dac_atten, int8_t input_type)
{
  poll = 0;     // used in input_sample() and output_sample() functions
  // allocate memory for ping pong buffers
  outptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  inptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  procptr = (int16_t *)malloc(BUFCOUNT*sizeof(int16_t));
  USTIMER_init();

  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_0, PINMUX_MCASP_MASK_0, PINMUX_MCASP_VAL_0);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_1, PINMUX_MCASP_MASK_1, PINMUX_MCASP_VAL_1);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_2, PINMUX_MCASP_MASK_2, PINMUX_MCASP_VAL_2);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_4, PINMUX_MCASP_MASK_4, PINMUX_MCASP_VAL_4);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_5, PINMUX_MCASP_MASK_5, PINMUX_MCASP_VAL_5);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_10, PINMUX_MCASP_MASK_10, PINMUX_MCASP_VAL_10);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_11, PINMUX_MCASP_MASK_11, PINMUX_MCASP_VAL_11);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_18, PINMUX_MCASP_MASK_18, PINMUX_MCASP_VAL_18);
  EVMOMAPL138_pinmuxConfig(PINMUX_MCASP_REG_19, PINMUX_MCASP_MASK_19, PINMUX_MCASP_VAL_19);

  // replaces I2C_init();
  *( volatile uint32_t* )(0x01C22024) = 0;
  *( volatile uint32_t* )(0x01C22030) = 2;
  *( volatile uint32_t* )(0x01C2200C) = 5;
  *( volatile uint32_t* )(0x01C22010) = 5;
  *( volatile uint32_t* )(0x01C22024) |= 0x20;
 
  CSR = 0x0000; // disable interrupts globally while initialising
                // GIE is bit 0 of CSR register

  L138_init_aic3106_registers(fs, adc_gain, dac_atten,input_type);
  L138_init_pcm3168a_registers();
  L138_init_src4392_registers();

  L138_init_mcasp_edma();

  // clear any pending interrupts within EDMA3CC
  EDMA_3CC_ICR = 0x0007; // writing to ICR affects IPR
  // associate event n with interrupt 4 by writing n into LSBs of INTMUX1
  // LSBs of INTMUX1 are literally associated with INT4
  // in this case n=8 (EDMA3CC   event)
  INTC_INTMUX1 = 0x00000008;

  ISTP = (unsigned int)vectors;
  // enable TCC = 0 and TCC = 1 EDMA3 interrupts by setting bits 0 and 1 in IESR
  EDMA3_IESR = 0x0003;
  EDMA3_DRAE1 = 0x0003;

  // clear all pending interrupt flags
  // interrupt clear register ICR is used to clear bits in interrupt flag register IFR
  ICR = 0xFFF0;  // ICR bits 3, 2, 1, and 0 are reserved, read as 0, write has no effect
  IER |= 0x12;  //enable NMI (bit 1) and INT4 (bit 4)
  
  CSR |= 0x01;  // enable interrupts globally
  //L138_init_LCDK_DIP();

}

If I have used the "syntaxhighlighter" correctly, differences will be highlighted. With serializer 9, the code gets stuck at line 246. I can't see why as with serializer 13, the code works fine and I have set them up the same in each of the two cases.

I have been configuring the MCASP based on "SPRU041J" so hopefully this is the correct document.

Any help would be greatly appreciated,

James

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c6748 EDMA