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McASP Question About DMA Servicing?

Other Parts Discussed in Thread: OMAP-L137

I'm reading the documentation before I start writing code and I'm not sure about something. 

http://www.ti.com/lit/ug/sprufm1/sprufm1.pdf 

For transmit operations through the DMA port, the DMA/CPU should write to the same XBUF DMA port
address to service all of the active transmit serializers. In addition, the DMA/CPU should write to the XBUF
for all active transmit serializers in incremental (although not necessarily consecutive) order. For example,
if serializers 0, 4, 5, and 7 are set up as active transmitters, the DMA/CPU should write to the XBUF DMA
port address four times with data for serializers 0, 4, 5, and 7 upon each transmit data ready event. This
exact servicing order must be followed so that data appears in the appropriate serializers.

Does that mean that for a OMAP-L137 I write to address 0x01D0 6000 (www.ti.com/.../omap-l137.pdf page 24 also page 120) four times? Or do I need to write to address 0x01D0 6000 + what ever offset my XBUF RBUF lands on? If the first one is true, I should what tells me when to write each of the four times. Figure 27 of sprufm1 implies that you get one EVT per time lost for all serializers which contradicts the first statement where it seems to imply you get as many EVT as active serializer.

Second question:

I cannot figure out the difference of 

WNUMEVT Write word count per DMA event (32-bit). When the Write FIFO has space for at least WNUMEVT
words of data, then an AXEVT (transmit DMA event) is generated to the host/DMA controller. This
value should be set to a non-zero integer multiple of the number of serializers enabled as
transmitters. This value must be set prior to enabling the Write FIFO.

This kind of implies, in my case, this value could be 1, 2, 3,.... since I only have one transmit serializer active. For the EVMOMAP137, BUF5 is the pne to transmit for the AIC3106.

It feels like AXEVT  and "transmit DMA event from the McASP" are different things. So I can write 16 samples to 0x01D0 6000 and the FIFO will move one at  time to the serializer and at some point I will get a notification that there is space for 16 more. Is this assumption correct? If that is true how to you write 16 samples to this address? 

WNUMDMA Write word count per transfer (32-bit words). Upon a transmit DMA event from the McASP, WNUMDMA words are transferred from the Write FIFO to the McASP. This value must equal the number of McASP serializers used as transmitters. This value must be set prior to enabling the Write FIFO.

Last, what is the size of the AFIFO?

  • Hi,

    Thanks for your post.

    To answer your first question:

    Yes, upon each transmit data ready event the DMA/CPU will write to the XBUF DMA port address (0x01D0 6000) four times with data in the same servicing order for the serializers  0, 4, 5, and 7 being setup as active transmitters. At a time, you can write the data to XBUF  mapped to only one active serializers and if you use multiple active serializers, you have to write each time the data to XBUF DMA port address four times mapped for the respective serializers in the same servicing order being setup.

    To answer your second question:

    Yes, you are right, AXEVT (transmit DMA event) context used in "WNUMEVT" and the "transmit DMA event" context used in "WNUMDMA" are different. To make you clear, please see the explanation below:

    When the Write FIFO is enabled, there are two transmit DMA requests, one initiated from McASP sends to AFIFO which in turn, AFIFO again sends to host/DMA controller. Here the context "AXEVT" used in WNUMEVT which is a transmit DMA event generated from AFIFO to the host/DMA controller and the context "transmit DMA event" used in WNUMDMA is generated from McASP to AFIFO. Hope it is clear now. To get more clarity on the sequence flow, please see below:

    "transmit DMA event" context used in WNUMDMA:

    If the Write FIFO is enabled, upon a transmit DMA request from the McASP to WFIFO, if WNUMDMA 32-bit words are available in WFIFO, it immediately writes to the McASP , if incase, it is not, the WFIFO waits until the WNUMDMA 32-bit words are available in WIFIFO. Once this condition is met, it writes WNUMDMA words to the McASP.

    "AXEVT" context used in WNUMEVT:

    If the Write FIFO has space to accept WNUMEVT 32-bit words, it generates a transmit DMA request from WFIFO to the host/DMA controller and then waits for a response. The host/DMA controller writes the requested WNUMEVT words to the WFIFO and WFIFO checks again to see if there is space for WNUMEVT 32-bit words. If there is space, it generates another transmit DMA request to the host/DMA controller, and so on. In this way, the Write FIFO will attempt always to stay filled.

    Hope the above explanation would clarify you the difference between the transmit DMA event context used in both WNUMDMA and WNUMEVT. If you need more explanation, please check sections 2.4.4.1 and 2.4.4.1.1 from the below:

    http://www.ti.com/lit/ug/sprufm1/sprufm1.pdf

    To address your last question,

    the maximum AFIFO size should be 256 bytes which is 64 32-bit words for 16 serializer (AXR data pins) and for each serializer data pin, it should be four 32-bit words.

    Thanks & regards,

    Sivaraj K

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  • It really does thank you very much. Although writing the code is the  true goal I found that is a lot easier to refer to the documentation first.

    The only thing is not clear to me, and thank you for your patience, is question number one. 

    "upon each transmit data ready event the DMA/CPU will write to the XBUF DMA port address (0x01D0 6000) four times with data in the same servicing order for the serializers  0, 4, 5, and 7 being setup as active transmitters."

    If you get one AXEVT how do I know when to write each of the four times? Is there another flag that paces these 4 writes to the same address or do I write 4 samples, for each serializer, in consecutive addresses from 0x01D0 6000. So, if 4 channels at 16 bit each I will end up writing a word of 4 x 16 bits. Well it may actually need to be 4x32 bits words, one for the left channel and one for the right.

    Another question, which is the address for the DMA port for RX and which is for TX? the documentation states the same address.

    ?

  • I think I figured it out from another post.

    "You should set up the EDMA to write the required number of bytes (3*4=32) representing data for all active transmit serializers in incrementing order."

    From <e2e.ti.com/.../264455&gt;

    I will give it a try and post back. If this is wrong please let me know so I don't chase my own tale for too long.

    Since the documentation is giving the same address for AXEVT and AREVT, I'm guessing that I can write and read from the same address but such events will be queue up and paced with when the transfer is complete for either RX or TX. Does that make sense?
  • Hi,

    There is a XRDY event which would tell you when to write to the XBUF DMA port address and upon each transmit data ready event (XRDY) the DMA/CPU will write to the XBUF DMA port address four times individually to the same address 0x01D0 6000 in the same servicing order for the serializers 0,4,5 and 7 one by one and each time but the data meant for the desired serializer may be different but write to the same 0x01D0 6000 address.

    For second question, the address for the RBUF and XBUF DMA port address would be same for McASP1 which is 0x 01D0 6000.

    Thanks & regards,

    Sivaraj K

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  • Hi,

    Yes, you are right and you could use the same address for AXEVT and AREVT to read and write on the same.

    Thanks & regards,

    Sivaraj K

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