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SDK 1.1.0.8 EtherCAT update. ICEv2.J4.Pin21

Shingo Fujiwara
Intellectual 470 points

Update was added some board specific implementations.

I want to know that these implementations don't need to original board.

And I want to know these setting is what to do.

tiescbsp.h

#define PDI_ISR_EDIO_NUM    7 //GPMC_CSN(2) -> pr1_edio_data_out7 for ICEv2.J4.Pin21

tiescbsp.c

bsp_clear_digio_out(PDI_ISR_EDIO_NUM);
bsp_write_byte((1 << PDI_ISR_EDIO_NUM), ESC_ADDR_TI_PDI_ISR_PINSEL);




  • 0
    TI__Mastermind 47651 points

    Hi,

    This is an optional feature we added to 1.1.0.8 implementation, you can find some details here

    processors.wiki.ti.com/.../AM335x_EtherCAT_firmware_API_guide

    PDI ISR DIGIO pin selection register   0x0E0A             
          0-7  R/W  R/W 
    0     		 PDI ISR DIGIO pin selection register, selects one of pr1_edio_data_outN pins as PDI ISR hw pin, configure 255 to disable. Set corresponding bitmask to enable. Application needs to configure pinmux correctly for this to work

    For ICE board, we are configuring pr1_edio_data_out7 and PDI ISR h/w pin. If your application does not require this

    You can do the following

    bsp_write_byte(0xff, ESC_ADDR_TI_PDI_ISR_PINSEL);

    and do not configure pinmux to select pr1_edio_data_outN